An acquisition detector and method include a preamble detector configured to search in a plurality of symbols for a preamble match with a known preamble pattern when a power level of the input signal exceeds a determined noise threshold. The acquisition detector further includes a frame delimiter detector configured to search in the plurality of symbols for a frame delimiter match with a known frame delimiter pattern when the preamble match is identified and the power level of the input signal exceeds a determined noise threshold.

An acquisition detector and method include a preamble detector configured to search in a plurality of symbols for a preamble match with a known preamble pattern when a power level of the input signal exceeds a determined noise threshold. The acquisition detector further includes a frame delimiter detector configured to search in the plurality of symbols for a frame delimiter match with a known frame delimiter pattern when the preamble match is identified and the power level of the input signal exceeds a determined noise threshold.

A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively holds or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

A receiving circuit, a transmission circuit and a system capable of reducing the effect of noise are provided. The receiving circuit includes: a pulse width detection unit which determines whether or not the pulse width of a pulse signal outputted based on comparison between a received-signal voltage and a reference voltage is smaller than a predetermined width; a reference voltage setting unit which, when the pulse width is smaller than the predetermined width, sets the reference voltage to be equal to or higher than a predetermined voltage; and an output control unit which, when the pulse width is equal to or larger than the predetermined width, causes a digital signal based on the pulse signal to be outputted or, when the pulse width is smaller than the predetermined width, performs control not to output the digital signal.

A method for processing an electrical signal comprises receiving an electrical signal comprising a frequency modulated signal encoding digital data; sampling a first portion of the electrical signal to obtain a plurality of samples to obtain a first sample set; determining an index value from the first sample set by assigning a value to each sample in the first sample set based upon an amplitude of the sample; comparing the determined index value with a plurality of predetermined index values to identify a first output value from a plurality of predetermined output values, each of the predetermined index values corresponding to one of the plurality of predetermined output values; and outputting an indication of the output value. Each of the predetermined output values indicates a respective frequency modulation encoded value and the first output value indicates a frequency modulation encoded value within the first portion of the electrical signal.

Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.

The present disclosure relates to a method for demodulating a frequency modulated signal of a PMA standard wireless charging device, including: (1) reading coil signals, sampling the coil signals, and counting cycles; (2) extracting a frequency change according to a change in a cycle count; (3) determining data according to the frequency change and a frequency duration and outputting the data; and (4) splicing the outputted data. With the method, a demodulation part does not require a complex analog circuit, and the highest frequency desired at a digital circuit part is only 4 MHz. Moreover, at this frequency, there is only a simple addition operation, and the main operating frequency is below 236 KHz.

A method of transmitting a Physical Layer Convergence Procedure (PLCP) frame in a Very High Throughput (VHT) Wireless Local Area Network (WLAN) system includes generating a MAC Protocol Data Unit (MPDU) to be transmitted to a destination station (STA), generating a PLCP Protocol Data Unit (PPDU) by adding a PLCP header, including an L-SIG field containing control information for a legacy STA and a VHT-SIG field containing control information for a VHT STA, to the MPDU, and transmitting the PPDU to the destination STA. A constellation applied to some of Orthogonal Frequency Division Multiplex (OFDM) symbols of the VHT-SIG field is obtained by rotating a constellation applied to an OFDM symbol of the L-SIG field.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

A data carrier apparatus includes a duty detector configured to determine a duty ratio of each pulse of a pulse signal that is received, a frequency detector configured to determine a period of each pulse of the pulse signal, and a demodulator configured to determine a value of data being carried by the pulse signal based on a determination result of the duty detector unit and a determination result of the frequency detector.