A semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder. The decoder includes a first circuit. The first circuit is configured to operate in synchronization with a clock signal. The first circuit is configured to perform image processing. A circuit configuration of the first circuit can be changed. Clock gating is performed on the first circuit to prevent the clock signal from being input to the first circuit when the circuit configuration of the first circuit is being changed. A broadcasting system including the semiconductor device is also provided.

An apparatus and method for channel switching comprising encapsulating a plurality of IP datagrams associated with a plurality of real time audio/visual (A/V) streams or a plurality of file objects onto a plurality of MPE sections; inserting the plurality of MPE sections into one of a plurality of elementary streams; and multiplexing the plurality of elementary streams associated with the plurality of real time A/V streams or the plurality of file objects into a plurality of non-consecutive bursts, wherein the plurality of elementary streams are adjacent in a channel line-up. In one aspect, the plurality of non-consecutive bursts is transmitted to a DVB-H receiver with a limited memory size for enabling fast channel switching. In one aspect, the channel line-up is presented in an electronic service guide (ESG).

A method includes receiving, from a first device at a second device, first input corresponding to selection of a previous channel option. The method includes, responsive to the first input, sending list data to a display device coupled to the second device, where the list data enables a display of a list of previously displayed channels. The list includes multiple elements and a selection indicator associated with a first element of the list. Each element of the multiple elements corresponds to a previously displayed channel. The method includes receiving, from the first device, second input corresponding to selection of a next channel option. The method also includes sending updated list data based on the second input to the display device. The updated list data updates the display to change an association of the selection indicator from the first element to a second element of the list.

An apparatus and method for channel switching comprising encapsulating a plurality of IP datagrams associated with a plurality of real time audio/visual (A/V) streams or a plurality of file objects onto a plurality of MPE sections; inserting the plurality of MPE sections into one of a plurality of elementary streams; and multiplexing the plurality of elementary streams associated with the plurality of real time A/V streams or the plurality of file objects into a plurality of non-consecutive bursts, wherein the plurality of elementary streams are adjacent in a channel line-up. In one aspect, the plurality of non-consecutive bursts is transmitted to a DVB-H receiver with a limited memory size for enabling fast channel switching. In one aspect, the channel line-up is presented in an electronic service guide (ESG).

A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

An imaging device and an electronic apparatus including an imaging device are provided. The imaging device includes a substrate and a photoelectric conversion film disposed above the substrate. A first pixel includes a first photoelectric conversion film region, first and second photoelectric conversion regions formed in the substrate, and a vertical transistor for the first photoelectric conversion element. A second pixel includes a second photoelectric conversion film region, first and second photoelectric conversion regions formed in the substrate, and a vertical transistor for the first photoelectric conversion element. The imaging device also includes a first floating diffusion. The first floating diffusion is shared by the first photoelectric conversion regions of the first and second pixels. A portion of the first photoelectric conversion regions of the respective pixels is between a light incident surface of the substrate and the vertical transistor for the respective pixel.

An image processing apparatus, comprising a memory that stores first image data, and a processor that includes an image associated information processing section, wherein the image associated information processing section, for the image data of a single frame that has been taken at a plurality of shooting conditions, within the first image data that has been stored in the memory, acquires image region information, relating to an image region in which shooting is carried out at different shooting conditions, and image associated information of the image region, associates the image region information and the image associated information and subjects the first image data to image processing, and generates second image data.

A method for displaying an animation by a display chip of an electronic device, which includes a non-volatile memory and a random-access memory. The display chip includes a video output register and a display register. The method includes a first static programming phase including configuring the video output register; writing n images in the memory, n being an integer higher than or equal to two; writing into the memory of a plurality of nodes, such that each node includes the address in the memory of at least one portion of an image, as well as the address of the following node in the memory, the last node including the address in the random-access memory of the first node; and configuring the display register. The method also includes a second phase in which the n images are read by the display chip by the display register, to display the animation.

A method includes receiving, at a computing device, input indicating a request to view a list. The list includes multiple elements, each of the elements corresponding to respective video content. The method also includes sending the list to a display device in response to the request, where the elements of the list are ordered based on a display order of the respective video content.

Described herein are systems and methods for providing hardware based security to software applications in a television receiver. The system can include a television receiver having a trusted hardware environment that includes a security processor and a standard environment that includes an application processor. The security processor can ensure that at least a portion of the software application executed by the application processor is secure. A portion of the software application code can be placed in an interrupt service routine memory space. During execution of the software application, the security processor can security check the portion of the software application in the interrupt service routine memory space, making it trusted code. The security processor can force the application processor to execute the trusted code by triggering an interrupt. Such forced execution can allow the security processor to not only ensure that code is trusted, but that it is executed.