An image sensor may include image pixels arranged in rows and columns. The image pixels may include respective overflow transistors and overflow capacitors and be configured to generate overflow charge during image acquisition. The overflow charge may be generated in a rolling manner on a row-to-row basis by repeatedly activating the overflow transistors and transfer transistors. Row control circuitry may be configured to provide a final synchronous overflow and transfer transistor activation across all of the pixel rows to provide a uniform overflow charge integration time period across all of the pixel rows. Row control circuitry may include a control signal generation circuit configured to generate control signals having full assertions in a first mode and partial assertions for the final synchronous overflow and transfer transistor activation in a second mode.

A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.

A solid-state image pickup device is provided which can inhibit degradation of image quality which may occur when a global electronic shutter operation is performed. A gate drive line for a first transistor of gate drive lines for pixel transistors is positioned in proximity to a converting unit.

Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out.

A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.

A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

An image sensor may include image pixels arranged in rows and columns. The image pixels may include respective overflow transistors and overflow capacitors and be configured to generate overflow charge during image acquisition. The overflow charge may be generated in a rolling manner on a row-to-row basis by repeatedly activating the overflow transistors and transfer transistors. Row control circuitry may be configured to provide a final synchronous overflow and transfer transistor activation across all of the pixel rows to provide a uniform overflow charge integration time period across all of the pixel rows. Row control circuitry may include a control signal generation circuit configured to generate control signals having full assertions in a first mode and partial assertions for the final synchronous overflow and transfer transistor activation in a second mode.

Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out.

Image sensors may include image sensor pixels that support high dynamic range (HDR) global shutter function. An image sensor pixel may include a photodiode that is coupled to multiple storage gate nodes via respective charge transfer gates. Each of the multiple storage gate nodes may be configured to store charge corresponding to different exposure periods. The storage gate nodes may be coupled in parallel or in series with the photodiode. Charge from the different exposure times can then be merged to produce a high dynamic range image signal.

An image sensor pixel may include a photodiode, a charge storage region, a floating diffusion node, and a capacitor. A first transistor may be coupled between the photodiode and the charge storage region. A second transistor may be coupled between the charge storage region and the capacitor. The photodiode may generate image signals corresponding to incident light. Multiple image signals may be summed at the charge storage region. The second transistor may determine a portion of the image signal that may be sent to the capacitor for storage. The portion of the image signal that is sent to the capacitor may be a low gain signal. A remaining portion of the image signal may be a high gain signal. The image sensor pixel may also include readout circuitry that is configured to readout low and high gain signals stored at the floating diffusion node in a double-sampling readout operation.