A circuit board includes a first insulating structure, a first redistribution layer, a second insulating structure, and a second redistribution layer. The first insulating structure has an upper surface and includes a first liquid crystal polymer layer. The first redistribution layer is disposed on the upper surface of the first insulating structure. The second insulating structure is disposed on the upper surface of the first insulating structure and covers the first redistribution layer. The second insulating structure has a top surface opposite to the upper surface and includes a second liquid crystal polymer layer. The second redistribution layer is disposed on the top surface of the second insulating structure.

A metal-ceramic substrate (1) comprising an insulating layer (11) comprising a ceramic and having a first thickness (D1), and a metallization layer (12) bonded to the insulation layer (11) and having a second thickness (D2),
wherein the first thickness (D1) is less than 250 μm and the second thickness (D2) is greater than 200 μm and wherein the first thickness (D1) and the second thickness (D2) are dimensioned such that a ratio of an amount of the difference between a thermal expansion coefficient of the metallization layer (12) and a thermal expansion coefficient of the metal-ceramic substrate (1) to a thermal expansion coefficient of the metal-ceramic substrate (1)
has a value less than 0.25, preferably less than 0.2 and more preferably less than 0.15 or even less than 0.1.

A fluorine-containing substrate, a copper clad laminate, and a printed circuit board are provided. The fluorine-containing substrate includes a reinforcing material layer and a fluorine-containing resin layer. The reinforcing material layer includes a substrate and a first inorganic filler. The first inorganic filler is attached on the substrate and is dispersed in the reinforcing material layer. The particle size of the first inorganic filler ranges from 0.02 μm to 1 μm. The reinforcing material layer is covered by the fluorine-containing resin layer. The fluoride resin layer includes a second inorganic filler whose particle size ranges between a value larger than 1 μm and 100 μm.

A component carrier has a stack including a plurality of electrically insulating layer structures and at least one electrically conductive layer structure, wherein two of the at least two electrically insulating layer structures form a dielectric double layer made of two different materials; a through-hole extending through the double dielectric layer; and an electrically conductive material filling at least a part of the through-hole. A method of manufacturing a component carrier is also disclosed.

Described is a metal-insulator substrate, which provides a structuring of the metallization for direct cooling. Furthermore, a process for manufacturing this metal-insulator substrate is described.

A light emitting module and the like having a higher heat-dissipation effect includes a light emitting element mounting substrate, one or more light emitting elements, a heatsink including a through-hole in a position corresponding to a screw hole, a bolt screwed in the screw hole and fastening the heatsink and a metal plate or a full thread and a nut for the fastening. In the light emitting element mounting substrate, the metal plate, an insulating layer, and an electrode layer on which the one or more light emitting elements are mountable are stacked in this order. The metal plate includes a bottomed screw hole opened at a surface opposite to a surface in contact with the insulating layer. The bolt or the full thread and the nut have a heat conductivity equal to or greater than that of the metal plate.

A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance≤(0.9×T1.sup.2/first distance), and/or (1.1×T1.sup.2/first distance)≤depression formation distance<second distance.

A substrate (1, 10) for electrical circuits, comprising at least one metal layer (2,3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2,3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a, 6a, 6b, 6b) to the metal layer (2,3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a, 6a, 6b,6b).

The present invention proposes a carrier substrate (1) for electrical components (13), the carrier substrate (1) having a component side (4) and a cooling side (5) which is opposite the component side (4) and has a cooling structure (30), the carrier substrate (1) comprising a primary layer (10) which faces the component side (4) and is produced from ceramic for electrical insulation, and a secondary layer (20) which faces the cooling side (5) for stiffening the carrier substrate (1), characterized in that a metallic intermediate layer (15) is arranged between the primary layer (10) and the secondary layer (20) for heat transfer from the component side (4) to the cooling side (5), the metallic intermediate layer (15) being thicker than the primary layer (10) and/or the secondary layer (20).

A semiconductor device and a method for producing a carrier element suitable for a semiconductor device are disclosed. In an embodiment a semiconductor device includes a carrier element including a carrier layer having a first depression extending from a first main surface of the carrier layer in a direction of a second main surface of the carrier layer opposite the first main surface and a metal substrate and an electrically insulating layer on at least a portion of the metal substrate, a first electrically conductive filling component arranged in the first depression in a form-fitting manner, the electrically insulating layer being arranged between the metal substrate and the first filling component and a semiconductor chip arranged on the carrier element, wherein the electrically insulating layer is an anodization layer.