A through-hole via penetrating, in a thickness direction, through a circuit board provided with multiple wiring layers in which a conductor pattern is formed on a surface of an insulating layer, wherein the through-hole via has a first through-hole conductor that is disposed inside a hole penetrating through the circuit board and that is formed from a conductor; a second through-hole conductor that is disposed inside the hole so as to be spaced, in a circumferential direction of the hole, from the first through-hole conductor; a first land portion that connects the first through-hole conductor to the conductor pattern on one insulating layer; and a second land portion that connects the first through-hole conductor with the second through-hole conductor on another insulating layer different from the one insulating layer.

A printed circuit board (PCB) core structure is provided for the transition of signals from one side of a PCB to an opposing side of the PCB. The PCB core structure may include a laminated core including an inner core including a plurality of conductive layers (N layers), a first dielectric layer, a first conductive trace disposed over the Nth conductive layer on a first side of the laminated core. The PCB core structure may also include a signal via extending from a first conductive layer to an Nth conductive layer through the laminated core, the signal via configured to connect the first conductive trace to a pin or a second conductive trace on a second side of the laminated core. The PCB core structure may also include a shielding structure surrounding the signal via and partially extending from the first conductive layer to the Nth conductive layer. The PCB core structure may also include a cavity removing a portion of the shielding structure in the Nth conductive layer and filled with a dielectric material. The cavity filled with the dielectric material prevents the first conductive trace from shorting to the shielding structure. The PCB core structure may be fabricated by using a single-lamination cycle.

Embodiments described herein relate to a method for modifying transmission line characteristics. The method may include: making a first determination of a null frequency of an input signal to a transmission line; performing an analysis to make a second determination of a wavelength of the input signal using, at least in part, the null frequency; making a third determination, based on the analysis, of a half wavelength of the input signal; calculating, based on the half wavelength, a total stub length; and adding a trace to a stub associated with a via, wherein the stub and the trace are a length that is at least a portion of the half wavelength of the input signal.

One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.

A multi-layer printed circuit board includes a base-layer metal, multiple middle metal layers and a top-layer metal. The middle metal layers are stacked on the base-layer metal sequentially. The top-layer metal is disposed on the middle metal layers. The base-layer metal, each middle metal layer and the top-layer metal are formed with multiple through holes respectively. Part of the middle metal layers are separately formed with multiple hole groups corresponding to the through holes. Each hole group includes multiple passing holes. The passing holes jointly surround a corresponding one of the through holes to form multiple connecting channels. Therefore, the multi-layer printed circuit board may reduce the cooling speed of the through holes to avoid an excessively low temperature of a pad to affect the soldering efficiency with keeping the high-frequency transmission and the signal isolation.

A system includes a power device unit coupled to a substrate. An upper cooling assembly is thermally coupled to an upper side of the substrate. A lower cooling assembly is thermally coupled to a lower side of the substrate. A gate driver unit is coupled to the upper cooling assembly. At least one upper via is formed through the upper cooling electrically coupling the gate driver unit to the power device unit. A capacitor unit is coupled to the lower cooling assembly. At least one lower via formed through the lower cooling assembly electrically coupling the capacitor unit to the power device unit.

A glass core, a multilayer circuit board, and a method of manufacturing a glass core that appropriately form copper wiring, and suppresses crack and the like, a glass core includes: a glass plate; a first metal layer provided on the glass plate; a first electrolytic copper plating layer provided on the first metal layer; a dielectric layer provided above the first electrolytic copper plating layer; a second metal layer provided on the dielectric layer; an electroless nickel plating layer provided on the second metal layer and having a phosphorus content of less than 5 mass %; and a second electrolytic copper plating layer provided on the electroless nickel plating layer.

A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.

Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.