Methods and apparatus for GDDR (Graphics Double Date Rate) memory expander using compression mount technology (CMT) connectors. A CMT connector with a dedicated pinout for GDDR-based memory is provided that enables end users and manufacturers to change the amount of GDDR memory provided with a GPU card, accelerator card, or apparatus having other form factors. Memory could also be replaced in the event of a failure. In addition, embodiments are disclosed that support a split channel concept where there could be multiple devices (e.g., GDDR modules) with dedicated signals routed to each module.

A wiring board includes: first and second insulating layers; a first wiring conductor layer located between the first and second insulating layers and including a first via land; a second wiring conductor layer located on the second insulating layer and including a second via land; a via hole penetrating from the upper to lower surfaces of the second insulating layer; and a via conductor located in the via hole and electrically connecting the first second via lands. The via conductor is located on the inner surface of the via hole and on the first via land via a first base layer containing nichrome and a second base layer located on the upper surface of the first base layer and containing the same metal as the via conductor. An alloy layer containing tin and nichrome is located between the first via land and the first base layer.

A circuit board has: an insulating substrate formed by plural ceramic insulating layers being layered on one another and having a first surface and a second surface on the opposite side to the first surface; a circuit conductor passing through the inside of the insulating substrate and positioned in a region from the first surface to the second surface; and at least one heating wire positioned in the insulating substrate. The heating wire is positioned in, among plural interlayer regions between the ceramic insulating layers, at least one interlayer region between the ceramic insulating layers and has a mesh shape having plural first through holes through which a portion of the circuit conductor passes and having plural second through holes through which the circuit conductor does not pass.

A high frequency filter includes: a multilayer substrate including a first substrate for which lands are provided, a second substrate for which lands are provided, and a third substrate for which lands are provided, the third substrate being sandwiched between the first substrate and the second substrate; a columnar conductor electrically connected to the lands in the multilayer substrate; and columnar conductors provided to surround the columnar conductor, electrically connected to a ground plane of the first substrate, and electrically connected to a ground plane of the second substrate. The spacing between the lands of the first substrate and the lands of the third substrate and the spacing between the lands of the second substrate and the lands of the third substrate are electrical lengths of 90 degrees or less at the cutoff frequency.

A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.

Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures.

Embodiments disclosed herein include package substrates for electronic packaging applications. In an embodiment, a package substrate comprises a first glass layer, where the first glass layer comprises a first via through the first glass layer, and the first via has an hourglass shaped cross-section. The package substrate may further comprise a second glass layer over the first glass layer, where the second glass layer comprises a second via through the second glass layer, and where the second via has the hourglass shaped cross-section. In an embodiment, the first via is electrically coupled to the second via.

The casing of an electronic control device includes a casing-side contact surface in contact with the end of a printed-circuit board. A cover includes a cover-side contact surface holding the end of the printed-circuit board together with the casing-side contact surface by being in contact with the end of the printed-circuit board. In the printed-circuit board, a held portion held between the casing-side contact surface and the cover-side contact surface is provided with a through-hole via.

A wiring substrate includes an insulating layer including resin and filler particles, conductor layers including an upper-layer conductor layer and a lower-layer conductor layer such that the insulating layer is sandwiched between the upper-layer and lower-layer conductor layers, and a penetrating conductor formed in the insulating layer such that the penetrating conductor is penetrating through the insulating layer and connecting the upper-layer and lower-layer conductor layers. The penetrating conductor is formed such that the penetrating conductor has a first length which is the maximum width of the penetrating conductor in the direction orthogonal to the thickness direction of the wiring substrate and the first length is 25 μm or less, and the insulating layer is formed such that the maximum particle size of the filler particles in a region within the distance of 40% of the first length from the penetrating conductor is 20% or less of the first length.

A method for designing PCB pads: using a drill bit of a first size to drill through a PCB from a first side; using a drill bit of a second size to back-drill a second side of the PCB so as to form a pyramid-shaped through hole; setting the connection means of a second layer and third layer of an inner layer of the PCB that comprises the pyramid-shaped through hole to full connection; and disposing a pad of a third size on a first layer of the inner layer, and disposing a pad of a fourth size on the last layer of the inner layer, wherein the fourth size is bigger than the third size, the fourth size is bigger than the second size, the second size is bigger than the first size, and the third size is bigger than the first size.