A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.

A wiring circuit board includes a first insulating layer; a conductive pattern disposed on one side of the first insulating layer in a thickness direction; and a metal support layer disposed on the other side of the first insulating layer in the thickness direction. The metal support layer has a terminal support portion supporting three terminals of the conductive pattern, a wiring support portion supporting a wiring of the conductive pattern, and a second wiring support portion supporting a second wiring of the conductive pattern. A thickness of each of the wiring support portions is thinner than a thickness of the terminal support portion.

A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed layer and the electrolytic plating layer and connecting the first conductor and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second portion and the third portion, the second portion has a first film and a second film electrically connected to the first film, and a portion of the first film is formed on the second film.

A method of manufacturing a printed circuit board a includes preparing an insulating substrate on which a first metal layer is formed, stacking a resist laminate having a plurality of layers on the first metal layer, forming an opening exposing a portion of the first metal layer by patterning the stacked resist laminate having the plurality of layers, forming a second metal layer on the exposed portion of the first metal layer, removing the patterned resist laminate having the plurality of layers, and etching at least another portion of the first metal layer.

A method for manufacturing a printed wiring board includes forming metal posts on a conductor circuit formed on a resin insulating layer, forming the outermost resin layer on the resin insulating layer such that the metal posts is embedded in the outermost resin layer, forming a mask at a dam formation site for a dam structure of the outermost resin layer to surround at least part of a pad group including the metal posts on the outermost resin layer, and reducing a thickness of the outermost resin layer exposed from the mask such that end portions of the metal posts are exposed from the outermost resin layer, that the metal posts form the pad group, and that the outermost resin layer has the dam structure forming part of the outermost resin layer and formed to surround at least part of the pad group including the metal posts.

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Fe.sup.+3 ions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described.

Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

A method of etching an electrically conductive layer structure during manufacturing a component carrier is provided. The method includes subjecting the electrically conductive layer structure to an etching composition having an etchant and a photosensitive compound to thereby form a recess in the electrically conductive layer structure; while, at least for a part of time, irradiating and/or heating the recess. In addition, an apparatus for etching an electrically conductive layer structure during manufacturing a component carrier, an etched electrically conductive layer structure and a component carrier are provided.

The present disclosure provides a circuit board including a first circuit layer, a dielectric layer on the first circuit layer, and a seed layer on the dielectric layer and directly contacting the first circuit layer, in which a top surface of the seed layer includes a levelled portion. The circuit board also includes a second circuit layer on the levelled portion of the seed layer, in which a grain boundary density of the second circuit layer is lower than that of a portion of the seed layer directly contacting the first circuit layer.

The present disclosure relates to a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a plurality of pads disposed on the insulating layer; and a plurality of insulating walls that are disposed on the insulating layer and cover side surfaces of the plurality of pads, respectively, but are not disposed on upper surfaces of the plurality of pads. The plurality of insulating walls are disposed to be spaced apart from each other on the first insulating layer.