A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.

Disclosed are an ultra-thin copper foil with a carrier foil and a method for manufacturing an embedded substrate by using the same, the ultra-thin copper foil with a carrier foil including: a carrier foil; a non-etching release layer on the carrier foil; a first ultra-thin copper foil layer on the non-etching release layer; an etch stop layer on the first ultra-thin copper foil layer; and a second ultra-thin copper foil layer on the etch stop layer.

Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed.

The method for manufacturing an insulated circuit board of the present invention includes: a ceramic/aluminum-joining step of joining an aluminum material to a ceramic substrate and thereby, forming an aluminum layer; a titanium material-disposing step of disposing a titanium material on a surface of the aluminum layer or the aluminum material in a circuit pattern shape; a titanium layer-forming step of performing a heat treatment in a state where the titanium material is laminated on the surface of the aluminum layer or the aluminum material and thereby, forming the titanium layer; and an etching treatment step of etching the aluminum layer on which the titanium layer is formed, into the circuit pattern shape.

A method for producing a metal foil comprising depositing metal onto an oxidizable substrate to form a metal film on the substrate; oxidizing the substrate at an interface between the metal film and the substrate; and removing the metal film from the substrate to yield a metal foil. A method for forming a thin metal film comprising pre-polarizing a single-crystal Si substrate by application of a potential which is negative of a potential at which Si oxidizes, which pre-polarization occurs in the presence of metal ions to form metal growth nucleation sites on the substrate, followed by application of a potential at which both oxidation of Si and electrodeposition of the metal occur to grow the metal film and oxidize the Si to SiOx, which potential is more positive than the potential applied in the pre-polarization step.

Methods of fabricating tamper-respondent electronic circuit structures and electronic assembly packages are provided which include, at least in part, a tamper-respondent sensor including one or more formed flexible layers of, for instance, a dielectric material, having opposite first and second sides, and circuit lines defining at least one resistive network. The circuit lines are disposed on at least one of the first side or the second side of the formed flexible layer(s). The formed flexible layer(s) with the circuit lines includes curvatures, and the circuit lines overlie, at least in part, the curvatures of the formed flexible layer(s). In certain embodiments, the formed flexible layer(s) may be one or more corrugated layers or one or more flattened, folded layers.

A copper plasma etching method according an exemplary embodiment includes: placing a substrate on a susceptor in a process chamber of a plasma etching apparatus; supplying an etching gas that include hydrogen chloride into the process chamber; plasma-etching a conductor layer that include copper in the substrate; and maintaining a temperature of the susceptor at 10 C. or less during the plasma-etching.

A wiring board includes an insulating layer, first and second pads provided on the insulating layer and including a first surface in contact with the insulating layer, a second surface opposite to the first surface, and a side surface connecting the first and second surfaces, respectively, and a protective insulating layer provided above the insulating layer. The first and second pads have a portion exposed inside an opening in the protective insulating layer. The first pad has a portion opposing the second pad without the protective insulating layer interposed between the first and second pads. A region of the second surface of the first and second pads exposed from the protective insulating layer is covered with a plating layer. A region of the side surface of the first and second pads exposed from the protective insulating layer is exposed from the plating layer.

Tamper-respondent electronic circuit structures, electronic assembly packages, and methods of fabrication are provided which include, at least in part, a tamper-respondent sensor. The tamper-respondent sensor includes one or more formed flexible layers of, for instance, a dielectric material, having opposite first and second sides, and circuit lines defining at least one resistive network. The circuit lines are disposed on at least one of the first side or the second side of the formed flexible layer(s). The formed flexible layer(s) with the circuit lines includes curvatures, and the circuit lines overlie, at least in part, the curvatures of the formed flexible layer(s). In certain embodiments, the formed flexible layer(s) may be one or more corrugated layers or one or more flattened, folded layers.

The present disclosure relates to a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a plurality of pads disposed on the insulating layer; and a plurality of insulating walls that are disposed on the insulating layer and cover side surfaces of the plurality of pads, respectively, but are not disposed on upper surfaces of the plurality of pads. The plurality of insulating walls are disposed to be spaced apart from each other on the first insulating layer.