A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.

A method for forming a printed circuit board includes: forming on a substrate a first conductive layer for a first edge connector pin and a first conductive layer for a second edge connector pin, wherein the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin are electrically coupled to one another via a first conductive layer for an electrical bridging element; electroplating a second conductive layer onto both the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin via a plating current conductor; and removing at least a portion of the electrical bridging element to electrically separate the first edge connector pin from the second edge connector pin.

A patterned article includes a unitary polymeric layer and a plurality of electrically conductive elements embedded at least partially in the unitary polymeric layer. Each electrically conductive element includes a conductive seed layer having a top major surface and an opposite bottom major surface in direct contact with the unitary polymeric layer, and includes a metallic body disposed on the top major surface of the conductive seed layer. The metallic body has a bottom major surface and at least one sidewall. The bottom major surface contacts the conductive seed layer. Each sidewall is in direct contact with the unitary polymeric layer and extends from the bottom major surface of the metallic body toward or to, but not past, a top major surface of the unitary polymeric layer. The conductive elements may be electrically isolated from one another. Processes for making the patterned article are described.

A circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask. The contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes. The solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 μm and is smaller than 5 μm.

A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.

A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.

A wiring substrate includes an insulating layer having a front surface and a back surface and at least two wiring parts that are disposed at least on the front surface of the insulating layer and that are insulated from each other. At least one of the wiring parts is electrically isolated on the insulating layer. Each of the wiring parts includes a conductive base layer disposed on the front surface of the insulating layer, a conductive layer disposed on a front surface of the conductive base layer, and a conductive covering layer arranged to cover at least a portion of a front surface of the conductive layer, at least a portion of a side surface of the conductive base layer, and at least a portion of a side surface of the conductive layer. The conductive base layer and the conductive layer overlap and coincide with each other in plan view.

A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.

Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.

A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.