A circuit board, including: a substrate; a first line layer, a first protective layer, a first conductive ink layer and a first conductive layer successively formed on the substrate; and a second line layer, a second protective layer, a second conductive ink layer and a second conductive layer successively formed on a second face opposite a first face. The first protective layer includes at least one first opening for exposing a first grounding line of the first line layer; and the orthographic projection of the first conductive ink layer on the substrate covers the orthographic projection of the first opening on the substrate. The second protective layer includes at least one second opening for exposing a second grounding line of the second line layer; and the orthographic projection of the second conductive ink layer on the substrate covers the orthographic projection of the second opening on the substrate.

Methods and structures are provided for implementing embedded wire repair for printed circuit board (PCB) constructs. A repair wire layer is provided within the PCB stack with reference planes on opposite sides of the repair wire layer. When a repair connection is required, an appropriate plated through hole (PTH) is drilled to form the repair connection using the repair wire layer.

In a printed wiring board, when a plurality of wiring base bodies are collectively stacked, a constituent material of a first layer of an insulating resin film has a low melting point, so that the first layer is easily melted. Therefore, thermal welding on an upper surface of the wiring base body is reliably performed, and the wiring base bodies are bonded to each other with high reliability.

A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.

A composite article includes a conductive layer with nanowires on at least a portion of a flexible substrate, wherein the conductive layer has a conductive surface. A patterned layer of a low surface energy material is on a first region of the conductive surface. An overcoat layer free of conductive particulates is on a first portion of a second region of the conductive surface unoccupied by the patterned layer. A via is in a second portion of the second region of the conductive surface between an edge of the patterned layer of the low surface energy material and the overcoat layer. A conductive material is in the via to provide an electrical connection to the conductive surface.

Disclosed is a stretchable substrate including: a via configured to provide an electrical connection between one surface and the other surface of the stretchable substrate; and a buffer shell positioned between the via and the stretchable substrate and having a Young's modulus value that is greater than a Young's modulus value of the stretchable substrate and smaller than a Young's modulus value of the via.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

The present invention relates to a patterned fiber substrate comprising: a fiber substrate; and a pattern consisting of a functional material and formed on the fiber substrate, wherein at least a part of the functional material that constitutes the pattern is present in inside of the fiber substrate, the fiber substrate has a contact angle of 100 to 170° with pure water on its surface, and the pattern has a narrowest line width of 1 to 3000 μm.

A multilayer substrate includes a laminate, first and second signal lines, first and second ground conductors, and interlayer connection conductors. The first and second signal lines extend along a transmission direction and include parallel extending portions that extend in parallel or substantially in parallel with each other. The first and second ground conductors sandwich the first and second signal lines in a laminating direction. The first and second ground conductors respectively include a first opening and a third opening between the signal lines when viewed from the laminating direction, and respectively include second openings and fourth openings disposed outside in a width direction orthogonal or substantially orthogonal to the transmission direction in the parallel extending portions when viewed from the laminating direction. The interlayer connection conductors are disposed in the transmission direction and at least between the signal lines.