The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate. The aqueous electrolytic composition comprises: (a) copper ions; (b) an acid; (c) a suppressor; and (d) a quaternized poly(epihalohydrin) comprising n repeating units corresponding to structure 1N and p repeating units corresponding to structure 1P: ##STR00001##

The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

A wiring substrate includes a first wiring layer; a first insulation layer including a reinforcement material and a first opening extending through the reinforcement material and exposing a partial region of an upper surface of the first wiring layer, in which an end of the reinforcement material projects in the first opening; a second insulation layer not including a reinforcement material, covering an upper surface of the first insulation layer, a wall surface of the first opening, and a first part of the partial region and an entire surface of the reinforcement material projecting in the first opening, and including a second opening exposing a second part of the partial region; and a second wiring layer including a wiring portion formed on an upper surface of the second insulation layer and a via portion formed in the second opening and connecting the wiring portion to the first wiring layer.

A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

A ceramic circuit board and a method of making are provided. The ceramic circuit board includes a substrate and a composite material layer. The composite material layer is formed on the substrate and comprises metal oxide powders and ceramic powders. The composite material layer has an interface layer which is transformed from the metal oxide powders by reduction and includes comprises zero-valent metal, lower-valent metal oxide and eutectic mixture reduced from the metal oxide powders of the composite material layer.

Various methods and systems are provided for forming a flexible circuit. In one example, a method includes forming a flexible circuit comprising a plurality of contact pads arranged into a plurality of rows, each contact pad of a given row electrically coupled to one another via electrical traces and each contact pad including a via, electroplating the flexible circuit, including electroplating each via, with at least a first material, and upon confirming connectivity of each via, cutting at least some of the electrical traces at least partially.

The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

In at least one illustrative embodiment, a printed circuit board may comprise at least one insulating layer, first and second conductive layers separated from one another by the at least one insulating layer, and a conductive via extending through the at least one insulating layer and electrically coupling the first and second conductive layers. The conductive via may include an annular via sidewall having an average radial thickness of at least 2.5 mils (0.0025 inches) and a conductive pad having an average thickness of no more than 3.2 mils (0.0032 inches).

An electromagnetic device and a method for manufacturing the same are disclosed. The electromagnetic device includes a base plate, a magnetic core, multiple transmission units, and connection layers. The base plate includes a central part defining multiple inner via holes and a peripheral part defining multiple outer via holes. An annular accommodating groove is defined between the central part and the peripheral part. The magnetic core is received in the annular accommodating groove. Transmission units are located on both sides of the base plate. Each transmission unit includes a transmission wire layer including multiple conductive wire patterns, and each conductive wire pattern bridges one inner via hole and one outer via hole. Each of the connection layers is set on one side of the transmission wire layer close to the base plate. At least one connection layer has a dielectric loss no larger than 0.02.