A method for preparing a conductive circuit can begin with the preparation of a non-conductive substrate having a top surface and a bottom surface, and then utilizing a pulse laser to create a top circuit pattern upon the top surface, a bottom circuit pattern upon the bottom surface, and a through hole connecting the top circuit pattern with the bottom circuit pattern. Subsequently, a conductive circuit is formed upon the top circuit pattern and the bottom circuit pattern and inside the through hole, wherein the conductive circuit is restricted from being formed upon the top surface outside of the top isolation region and the bottom surface outside of the bottom isolation region.

The present invention discloses a method for manufacturing a printed circuit board having an ultra-thin metal layer. The method discharges alkaline aliphatic amine gas and the nitrogen bubbled in the cupric sulfate solution via capacitive coupling in a vacuum, to generate low temperature plasma. The polyimide film and the epoxy resin board coated with fiberglass cloth are etched and the surface is treated to graft active groups, so as to increase the surface roughness and chemical activity. Subsequently, sputtering copper plating or chemical copper plating is directly conducted. The electroplating is conducted to thicken the copper film to a required thickness. The method of the invention not only does not need adhesive (adhesive free), but also has a high peeling strength. It can be used for the preparation of the flexible PCB, the rigid PCB, the multi-layer PCB, and rigid-flex PCB, having an ultra-thin metal layer.

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.

A manufacturing method of a substrate structure including vias includes the following steps. A substrate is provided, wherein a material of the substrate includes polyimide. An etching stop layer is formed on the substrate, wherein the etching stop layer covers two opposite surfaces of the substrate. A patterned process is performed on the etching stop layer to form a plurality of openings exposing a part of the substrate. An etching process is performed on the substrate to remove the part of the substrate exposed by the openings and form a plurality of vias.

A package substrate that prevents breakage of a core substrate is provided. A package substrate includes a core substrate made of a brittle material, at least one insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or in the insulating layer, the core substrate being exposed from an outer peripheral portion of the insulating layer, and the insulating layer being chamfered.

Method for forming a metal film includes forming an oxide layer on a to-be-treated surface of a to-be-treated object by bringing the to-be-treated surface into contact with a reaction solution containing fluorine and an oxide precursor, removing fluorine in the oxide layer, supporting a catalyst on the oxide layer by bringing the oxide layer into contact with a catalyst solution, and depositing a metal film on the oxide layer by bringing the oxide layer into contact with an electroless plating liquid.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A microelectronic substrate may be fabricated having a substrate core with at least one plated through hole extending therethrough, wherein the plated through hole includes a fluorescent conductive fill material which can be utilized to detect defects during the fabrication process. In one embodiment, the microelectronic substrate may be fabricated by forming a substrate core, forming a hole to extend from a first surface to an opposing second surface of the substrate core, forming a conductive material layer on a sidewall(s) of the substrate core hole, disposing a fluorescent conductive fill material to abut the conductive material layer and fill the remaining substrate core hole, illuminating an exposed portion of the fluorescent conductive fill material, and detecting anomalies in the light fluoresced by the exposed portion of the fluorescent conductive fill material.

A method for preparing a conductive circuit can begin with the preparation of a non-conductive substrate having a top surface and a bottom surface, and then utilizing a pulse laser to create a top circuit pattern upon the top surface, a bottom circuit pattern upon the bottom surface, and a through hole connecting the top circuit pattern with the bottom circuit pattern. Subsequently, a conductive circuit is formed upon the top circuit pattern and the bottom circuit pattern and inside the through hole, wherein the conductive circuit is restricted from being formed upon the top surface outside of the top isolation region and the bottom surface outside of the bottom isolation region.

A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.