A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

A one-surface groove for wiring is formed in a front surface 2a, opposite-surface grooves for wiring are formed in a back surface 2b by protruding core members, and communication parts for allowing the one-surface groove and the opposite-surface grooves to communicate with each other are formed to shape a board section 2 made of a non-conductive resin. After the core members are retracted, a conduction-side resin, which will become conductive, is shaped in the one-surface groove, the opposite-surface grooves, and the communication parts to form front-side wiring 3, communication wirings 4, and back-side wirings 5, whereby a wiring circuit component is provided.

A method for producing a glass substrate according to the present invention includes the steps of: (I) forming a through hole (11) in a glass sheet (10); (II) forming a resin layer (20) on a first principal surface of the glass sheet (10) using a resin composition sensitive to light having a predetermined wavelength λ.sub.1; (III) photoexposing an area of the resin layer (20) that covers the through hole (11) by irradiating the area with light U having the wavelength λ.sub.1 and applied from the direction of a second principal surface of the glass sheet (10); and (IV) forming a through-resin hole (21) by removing the area photoexposed in the step (III). The glass sheet (10) protects the resin layer (20) from the light U so as to prevent the resin layer (20) from being photoexposed by beams of the light U that are incident on the second principal surface of the glass sheet (10) in the step (III).

A wiring board includes an insulating base including a first principal surface, a second principal surface opposite to the first principal surface, and a first through hole penetrating the insulating base from the first principal surface to the second principal surface, a functional material provided inside the first through hole, a first insulating layer covering the first principal surface, and a first surface of the functional material, and a second insulating layer covering the second principal surface, and a second surface of functional material. A second through hole is formed in the first insulating layer, the functional material, and the second insulating layer, and a conductive layer is formed on a wall surface of the second through hole.

Disclosed are a method for fabricating a printed circuit board wherein through-holes are formed in an organic substrate, followed by forming micro-circuit patterns through sputtering and plating, whereby the printed circuit board has low permittivity properties and enables high-speed processing, and a printed circuit board fabricated thereby. The disclosed method for fabricating a printed circuit board comprises the steps of: preparing a base substrate; forming a through-hole perforating the base substrate; forming a thin seed layer on the base substrate and in the through-hole; forming a thin plate layer on the thin seed layer; and etching the thin seed layer and the thin plate layer to form a micro-circuit pattern, wherein the base substrate is one selected from an organic substrate, FR-4, and Prepreg.

A circuit board includes a baseboard, a first conductive circuit layer, a second conductive circuit layer, at least one through hole, and a number of conductive lines. The first conductive circuit layer includes a number of first conductive circuit lines formed on a first side of the baseboard. The second conductive circuit layer includes a number of second conductive circuit lines formed on a second side of the baseboard. The through hole is defined through the first conductive circuit layer, the baseboard, and the second conductive circuit layer. The number of conductive lines are formed in an inner wall of the through hole and spaced apart around the through hole. Each conductive line electrically couples one of the first conductive circuit lines to a corresponding one of the second conductive circuit lines.

A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having a 1.2 or more aspect ratio in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.

In some embodiments, a manufacturing process includes injection molding a palladium-catalyzed material into a substrate, forming a thin copper film over exterior and exposed surfaces of the substrate; ablating or removing copper film from the substrate to provide first, second and optional third portions of the copper film and ablated sections; electrolytically plating each portion to form metallic-plated portions; and ablating or removing the second portion in order to isolate the first portion. The metallic-plated first portion comprises a circuit portion of a molded interconnect device (MID), and where the metallic-plated third portion comprises a Faraday cage portion of a MID. A soft etching step may be included. A solder resist application step can be added, along with an associated solder resist removal step.

The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Disclosed herein is a method of forming vias in electrical laminates comprising laminating a sheet having a layer comprising a crosslinkable polymer composition to a substrate wherein the crosslinkable polymer composition has a viscosity at lamination temperatures in the range of 200 Pa-s to 100,000 Pa-s, forming at least one via in the crosslinkable polymer layer by laser ablation; and after the forming of the at least one via, thermally curing the crosslinkable polymer layer. According to certain embodiments the cross linkable polymer composition has a viscosity at lamination temperature of at least 5000 Pa-s. This method yields good lamination results, good via profiles, and good desmear results when such compositions are used and the via is laser ablated before cure.