A wiring board according to the present disclosure includes an insulation layer, and a wiring conductor positioned on the insulation layer. The wiring conductor includes a phosphorus-containing electroless copper-plating layer positioned on the insulation layer, a nickel-containing electroless copper-plating layer positioned on the phosphorus-containing electroless copper-plating layer, and an electrolytic copper-plating layer positioned on the nickel-containing electroless copper-plating layer.

A substrate for a printed circuit board according to an embodiment of the present invention includes a resin film and a metal layer stacked on at least one of surfaces of the resin film. An average diffusion depth of a main metal of the metal layer in the resin film is 100 nm or less after a weather resistance test in which the substrate is held at 150 C. for seven days. The average diffusion depth is preferably 80 nm or less before the weather resistance test.

A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.

According to an embodiment of the present invention, a substrate for a printed circuit board, the substrate including a resin film and a metal layer deposited on at least one surface of the resin film, includes a modified layer on the surface of the resin film on which the metal layer is deposited, the modified layer having a composition different from another portion, in which the modified layer contains a metal, a metal ion, or a metal compound different from a main metal of the metal layer. The content of a metal element of the metal, the metal ion, or the metal compound on a surface of the modified layer is preferably 0.2 atomic % or more and 10 atomic % or less.

A printed circuit board includes a base film having a main surface, and an electrically conductive pattern disposed on the main surface. A normal line of the main surface is along a first direction. The electrically conductive pattern includes a plurality of wiring portions disposed side by side along a second direction to be spaced apart from each other, the second direction being orthogonal to the first direction. The plurality of wiring portions include a first wiring portion and a second wiring portion that are each present at a corresponding one of both ends in the second direction and a plurality of third wiring portions that are present between the first wiring portion and the second wiring portion in the second direction.

A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.

A printed circuit board comprises a support structure, a conductive layer operably coupled to the support structure, a mask structure formed on the conductive layer, and a cover layer. The conductive layer comprises first and second portions of conductive material separated by a gap that defines a spacing between the first and second portions that does not contain conductive material. The mask structure defines first and second regions on the conductive layer. The first region is enclosed by a first boundary defined by the mask structure and includes the gap. The second region lies outside of the first boundary. The cover layer is sized to fit within the first region and comprises a laminatible insulating material that flows within the first region during lamination. During lamination, the first boundary prevents the laminatible insulating material from flowing into the second region, and the laminatible insulating material flows to fill the gap.

A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.