A method for producing a waveguide in a multilayer substrate involves producing at least one cutout corresponding to a lateral course of the waveguide in a surface of a first layer arrangement comprising one or a plurality of layers. A metallization is produced on surfaces of the cutout. A second layer arrangement comprising one or a plurality of layers is applied on the first layer arrangement. The second layer arrangement comprises, on a surface thereof, a metallization which, after the second layer arrangement has been applied on the first layer arrangement, is arranged above the cutout and together with the metallization on the surfaces of the cutout forms the waveguide.

An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

A method for connecting a flexible printed circuit (FPC) to a battery module and a cell supervision circuit board (CSCB) is provided. The method includes: providing a coil of a continuous, strip-shaped FPC; unwinding a first section of the FPC from the coil, positioning the first section of the FPC over a first contact portion of the battery module, and welding a conductive structure of the FPC in the first section to the first contact portion of the battery module; unwinding a second section of the FPC from the coil, positioning the second section of the FPC over a contact pad of the CSCB, and welding the conductive structure of the FPC in the second section to the contact pad of the CSCB; and separating the first section and second section of the FPC from the coil of the FPC.

A printed wiring board includes a first insulating layer, a conductor layer, and a second insulating layer. The conductor layer includes first and second circuits such that space is formed between the circuits, the first circuit has first and second side walls, the second circuit has third and fourth side walls such that the second wall faces the third wall, the first circuit has first, second and third portions, the second circuit has fourth, fifth and sixth portions such that the first and fourth portions, the second and fifth portions and the third and sixth portions face each other, the first circuit is formed such that the second wall of the second portion is recessed from the second wall of the first and third portions, and the first insulating layer has recess between the second and fifth portions such that the second insulating layer is filling the space and recess.

An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

The invention relates to a carrier arrangement (100; 500; 600; 700; 800; 900; 1000), and a method for producing a carrier arrangement. The method comprises: producing a layer (130; 530; 630; 730; 830; 930; 1030) on a surface (120; 520; 620; 720; 820; 920; 1020) of a carrier (110; 510; 610; 710; 810; 910; 1010), the layer comprising a first region (131; 531; 631; 731; 831; 931; 1031) and a second region (132; 532; 632; 732; 832; 932; 1032) connected to the first region, the first region covering a first surface region (121; 521; 621; 721; 821; 921; 1021) of the carrier and the second region covering a second surface region (122; 722; 922) of the carrier, detaching the second region of the layer from the carrier, the first region of the layer remaining on the first surface region of the carrier and not being separated from the second region, the layer being flexible in the detached second region.

The invention provides a printed circuit board (10) including a first electrically conductive track (210), wherein the printed circuit board (10) comprises a set (15) of two printed circuit board areas (100) both comprising a part of the first electrically conductive track (210), wherein printed circuit board (10) further comprises a perforation line (300) between the two printed circuit board areas (100) for customizing the printed circuit board (10) into two physically separated printed circuit board area comprising parts (1100), wherein the perforation line (300) is configured as a non-straight line, wherein the perforation line (300) comprises relative to one of the printed circuit board areas (100), and in a plane of the printed circuit board (10), a first projecting part (311) and a first recessed part (312), wherein the first recessed part (312) is recessed relative to the first projecting part (311), wherein the first electrically conductive track (210) is intercepted by the perforation line (300) at the first recessed part (312).

A circuit board includes at least two circuit board units stacked together. Each circuit board unit includes a substrate and a circuit layer. The substrate defines a conductive hole penetrating therethrough. The conductive hole provided with a conductor therein. One side of the substrate further defines a groove, the groove including a concave portion aligned with the conductive hole. The circuit layer includes a connection pad located in the concave portion. The connection pad is shaped as a conductive protrusion, which surrounds and is electrically connected to the conductor. The circuit layer is located in the groove, and the conductive hole is electrically connecting the circuit layers of the circuit board units.

A surface mounted Light Emitting Diode (LED) device includes a printed circuit board (PCB), at least one color LED chip mounted on the PCB, and a driving chip. The driving chip is mounted on the PCB and electrically connected to the at least one color LED chip to drive the at least one color LED chip. The driving chip has a signal input port and a signal output port. The signal input port is electrically connected to a signal input conductive pad, and the signal output port is electrically connected to a signal output conductive pad. The surface mounted LED device further includes a gap located between the signal input conductive pad and the signal output conductive pad for creating a space for a cutting apparatus to sever any conductive line through the gap, and making a manufacturing procedure of the surface mounted LED device easier.

This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.