A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.

A medical device with a capacitive sensing function includes a medical body having a syringe and a sensing circuit having an electrode, a protective film adhered to the medical body and including a plastic film, an electrode provided on the plastic film and opposite from the electrode of the medical body, and a capacitive sensor formed by the electrode of the medical body and the electrode of the protective film and being a part of the sensing circuit, wherein a capacitance value of the capacitive sensor changed under the condition of removing the protective film from the medical body, the sensing circuit being configured to detect the capacitance value and trigger corresponding function of the medical body.

An axial field rotary energy device has a PCB stator panel assembly between rotors with an axis of rotation. Each rotor has a magnet. The PCB stator panel assembly includes PCB panels. Each PCB panel can have layers, and each layer can have conductive coils. The PCB stator panel assembly can have a thermally conductive layer that extends from an inner diameter portion to an outer diameter portion thereof.

A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.

A radio-frequency device and a radio-frequency component thereof are provided. The radio-frequency component includes a signal transmission line and a first electrostatic protection module coupled to the signal transmission line. The first electrostatic protection module includes a first wire layer including a first wire coupled to the signal transmission line, a first cell layer disposed corresponding to the first wire layer and including a first conductive body and a plurality of first non-conductive portions, a first grounding layer coupled to the first wire layer and the first cell layer, a first dielectric layer disposed between the first wire layer and the first cell layer, and a second dielectric layer disposed between the first cell layer and the first grounding layer. A vertical projection of the first conductive line on the first dielectric layer at least partially overlaps with that of the first cell layer on the same.

An inhomogeneous dielectric medium high-speed signal trace system includes first and second ground layers. A first dielectric layer has a first dielectric constant and is located adjacent the first ground layer, and a second dielectric layer has a second dielectric constant that is different than the first dielectric constant and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first and second dielectric layer. A plurality of first vias extend between the first ground layer and the second ground layer and are spaced part from each other and the first differential trace pair. A plurality of second vias extend between the first ground layer and the second ground layer, are spaced part from each other and the first differential trace pair, and are located opposite the first differential trace pair from the plurality of first vias.

In one embodiment, a system includes a ground layer, a first layer, a second layer, and a plurality of vias. The first layer includes a first insulating material and a plurality of first metallic strips. The second layer includes a second insulating material and a plurality of second metallic strips. The plurality of vias electrically connect one or more of the plurality of first metallic strips of the first layer to one or more of the plurality of second metallic strips of the second layer. The plurality of first metallic strips of the first layer and the plurality of second metallic strips of the second layer form a plurality of capacitors and a plurality of conductors. Each capacitor is located in the first layer. Each conductor is partially located in the first layer and partially located in the second layer.

A printed circuit board (‘PCB’) including a substrate integrated waveguide (‘SIW’) formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.

The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil×8 mil cuts or indentations in the copper shape.