Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

Disclosed are a method and a structure for layout and routing of a PCB. The method includes: arranging signal lines, a power plane and a ground plane of the PCB in combination, where a portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines, to save routing spates. Layout of regions for the power supply, the ground and signal lines is appropriately designed, thereby improving the design density of a board, reducing the number of layers of the PCB, and saving cost.

A light emitting diode (LED) module may include a direct current (DC) voltage node formed on a first layer. The DC voltage node may be configured to sink a first current. One or more devices may be formed on the first layer configured to provide a second current to one or more LEDs. A device of the one or more devices may carry a steep slope voltage waveform. A local shielding area may be formed in a second layer directly below the DC voltage node and the one or more devices. The local shielding area may include a substantially continuous area of conductive material. A conductive via may extend through one or more layers. The conductive via may electrically connect the DC voltage node and the local shielding area.

Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.

A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

A circuit board includes a first body part, a second body part and a connection part. The first body part includes a first contact surface and has a multi-layered structure. The second body part includes a second contact surface, has a multi-layered structure, and includes a first signal line spaced apart from the second contact surface. The connection part includes a third contact surface between the first contact surface and the second contact surface, and connects the first body part and the second body part to each other.

Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.

An apparatus configured to measure electromagnetic radiation coupled from an image sensor integrated circuit (IC) to a nearby cell phone antenna has an image sensor PCB with the image sensor IC on a first side and image sensor decoupling capacitors disposed on a second side, the image sensor PCB disposed within a shielding box. The apparatus also has an image processor PCB with an image processor IC on a first side and at least one image processor decoupling capacitors, the image processor IC electrically coupled to the image sensor IC. The image processor IC is located outside the shielding box, and the at least one image processor decoupling capacitor is within the shielding box. In embodiments, the decoupling capacitors are shielded with separate, additional, metal covers.

A printed circuit board may comprise a first layer in which a first signal transmission path is formed, a second layer disposed in one surface direction of the first layer and including a first ground for providing a return current path for a signal transmitted from the first layer, a third layer in which a second signal transmission path is formed and a fourth layer disposed in the other surface direction of the third layer and including a second ground for providing a return current path for a signal transmitted from the third layer.

A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.