H05K2201/09363

ELECTRONIC ASSEMBLY

An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.

POWER DELIVERY NETWORK NOISE ISOLATION IN A COMPUTING DEVICE
20230262874 · 2023-08-17 ·

A system for power delivery network (“PDN”) isolation may include a multi-layer printed circuit board (“PCB”) in which a power distribution layer has a root conductive region and two or more branch conductive regions fanning out from the root conductive region. Each branch conductive region may be insulated from other branch conductive regions by a non-conductive region. Each branch conductive region may have at least one power delivery connection. Each of various electronic circuits mounted on the PCB and sharing the same PDN may be shorted to one of the branch conductive regions.

Electronic assembly

An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.

SINGLE LAYER RADIO FREQUENCY INTEGRATED CIRCUIT PACKAGE AND RELATED LOW LOSS GROUNDED COPLANAR TRANSMISSION LINE
20210368615 · 2021-11-25 ·

A novel and useful a single layer RFIC/MMIC structure including a package and related redistribution layer (RDL) based low loss grounded coplanar transmission line. The structure includes a package molded around an RF circuit die with a single redistribution layer (RDL) fabricated on the surface thereof mounted on an RF printed circuit board (PCB) via a plurality of solder balls. Coplanar transmission lines are fabricated on the RDL to conduct RF output signals from the die to PCB signal solder balls. The signal trace transition to the solder balls are funnel shaped to minimize insertion loss and maximize RF isolation between channels. A conductive ground shield is fabricated on the single RDL and operative to shield the plurality of coplanar transmission lines. The ground shield is electrically connected to a ground plane on the PCB via a plurality of ground solder balls arranged to surround the plurality of coplanar RF transmission lines and signal solder balls, and are operative to couple the ground shield to the ground plane on the PCB and provide an electrical return path for the plurality of coplanar transmission lines. Ground vias on the printed circuit board can be either located under the ground solder balls or between them.

EMC FILTER FOR A CONTROL DEVICE
20230328874 · 2023-10-12 ·

The invention relates to an EMC filter for a control device. The filter includes a multilayer circuit carrier comprising electrically conductive layers, in particular copper layers, and electrically insulating circuit board layers. According to the invention, the circuit carrier of the aforementioned type forms at least two filter capacitors, wherein in each case the filter capacitors are formed by electrically conductive layers that are formed in the circuit carrier and lie across from one another and/or extend parallel at a distance from each other.

Loading Pads for Impedance Management in Printed Circuit Board
20230319985 · 2023-10-05 ·

A printed circuit board (PCB) for three-dimensional (3D) packaging that may facilitate packaging multiple electronic components therein is provided. The PCB may include one or more loading pads formed around signal or ground vias to facilitate impedance control and reduce likelihood of signal distortion. The loading pads may be formed on a plane in a body of a dielectric layer configured to form the PCB.

SIDEWALL PLATING OF CIRCUIT BOARDS FOR LAYER TRANSITION CONNECTIONS
20230371177 · 2023-11-16 ·

A circuit board including: a first board material layer having a first planar surface and a first sidewall surface perpendicular to the first planar surface; a first conductive layer on the first planar surface; a second board material layer stacked on the first board material layer and having a second planar surface and a second sidewall surface perpendicular to the second planar surface; a second conductive layer on the second planar surface; and a plating on the first sidewall surface and the second sidewall surface and electrically connecting the first conductive layer and the second conductive layer.

Printed circuit board including ground line for canceling electromagnetic waves generated by power line, and electronic device including same
11464103 · 2022-10-04 · ·

A printed circuit board according to various embodiments of the present disclosure can include a first substrate layer, a dielectric layer stacked below the first substrate layer, and a second substrate layer stacked below the dielectric layer. The second substrate layer can include: a power line; a ground part disposed to have an isolated area along the power line; and a ground line which extends from the ground part so as to be disposed in the isolated area, and which separates the isolated area into a first area and a second area so as to generate electromagnetic waves for canceling the electromagnetic waves generated by a current flowing through the power line. Other embodiments are also possible.

Single layer radio frequency integrated circuit package and related low loss grounded coplanar transmission line

A novel and useful a single layer RFIC/MMIC structure including a package and related redistribution layer (RDL) based low loss grounded coplanar transmission line. The structure includes a package molded around an RF circuit die with a single redistribution layer (RDL) fabricated on the surface thereof mounted on an RF printed circuit board (PCB) via a plurality of solder balls. Coplanar transmission lines are fabricated on the RDL to conduct RF output signals from the die to PCB signal solder balls. The signal trace transition to the solder balls are funnel shaped to minimize insertion loss and maximize RF isolation between channels. A conductive ground shield is fabricated on the single RDL and operative to shield the plurality of coplanar transmission lines. The ground shield is electrically connected to a ground plane on the PCB via a plurality of ground solder balls arranged to surround the plurality of coplanar RF transmission lines and signal solder balls, and are operative to couple the ground shield to the ground plane on the PCB and provide an electrical return path for the plurality of coplanar transmission lines. Ground vias on the printed circuit board can be either located under the ground solder balls or between them.

Method and device for a high temperature vacuum-safe solder resist utilizing laser ablation of solderable surfaces for an electronic module assembly

A process for manufacturing an electronic component having attaches includes providing a first component having a first attach, forming trenches on a portion of the first attach with a laser to form a solder stop, and providing a second component comprising a second attach. The process further includes providing solder between the first attach and the second attach to form a connection between the first component and the second component, where the trenches contain the solder to a usable area. A device produced by the process is disclosed as well.