Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

The invention relates to an electronic board (1) comprising: a printed circuit (2) having a connection face (3) defining a plane (X, Y) comprising at least one transfer area (4), an electronic component (5) comprising at least one contact terminal (6), each contact terminal (6) being brazed or sintered on an associated transfer area (4) by means of a brazing joint or of a sintering joint (7), the electronic board being characterised in that an orthogonal projection of the contact terminal (6) of the electronic component (5) on the connection face (3) of the printed circuit does not overlap the associated area (4).

A wiring substrate includes an insulating substrate that is square in plan view, the insulating substrate having one main surface with a recess and an other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate and in a peripheral section of the insulating substrate. The external electrodes include first external electrodes and second external electrodes. In plan view, the first external electrodes are located at corners of the insulating substrate, and the second external electrodes are interposed between the first external electrodes. Each of the first external electrodes has a smaller area and a larger width in a direction orthogonal to each side of the insulating substrate than each of the second external electrodes.

A connection arrangement for forming a component carrier structure is disclosed. The connection arrangement includes a first electrically conductive connection element and a second electrically conductive connection element. The first connection element and the second connection element are configured such that, upon connecting the first connection element with the second connection element along a connection direction, a form fit is established between the first connection element and the second connection element that limits a relative motion between the first connection element and the second connection element in a plane perpendicular to the connection direction. A component carrier and a method of forming a component carrier structure are also disclosed.

An item may include fabric having insulating and conductive yarns or other strands of material. The conductive strands may form signal paths. Electrical components can be mounted to the fabric. Each electrical component may have an electrical device such as a semiconductor die that is mounted on an interposer substrate. The interposer may have contacts that are soldered to the conductive strands. A protective cover may encapsulate portions of the electrical component. To create a robust connection between the electrical component and the fabric, the conductive strands may be threaded through recesses in the electrical component. The recesses may be formed in the interposer or may be formed in a protective cover on the interposer. Conductive material in the recess may be used to electrically and/or mechanically connect the conductive strand to a bond pad in the recess. Thermoplastic material may be used to seal the solder joint.

The invention relates to an electronic board (1) comprising: a printed circuit (2) having a connection face (3) defining a plane (X, Y) comprising at least one transfer area (4), an electronic component (5) comprising at least one contact terminal (6), each contact terminal (6) being brazed or sintered on an associated transfer area (4) by means of a brazing joint or of a sintering joint (7), the electronic board being characterised in that an orthogonal projection of the contact terminal (6) of the electronic component (5) on the connection face (3) of the printed circuit does not overlap the associated area (4).

A multi-chip package may include a plurality of semiconductor chips and a printed circuit board (PCB). Each of the semiconductor chips may have an upper surface, a bottom surface, and a plurality of side surfaces. Circuit terminals may be arranged on the upper surface. A plurality of side bonding pads may be arranged on one or more selected side surface among the side surfaces. The semiconductor chips may be mounted on the PCB. The PCB may be configured to surround the selected side surface on which the side bonding pads may be arranged.

A substrate may be included in an electronic device. The substrate may include a first layer that may include a dielectric material. The first layer may define a substrate surface. The substrate may include a second layer optionally including the dielectric material. The second layer may be coupled to the first layer. A wiring trace may be located in the substrate. A recess may extend through the substrate surface, the first layer, and may extend through the second layer. A substrate interconnect may be located within the recess. The substrate interconnect may be at least partially located below the substrate surface. The substrate interconnect may be in electrical communication with the wiring trace.

An inductor component includes a component body having a mounting surface and a top surface and provided therein with a spiral inductor wiring line advancing in the extending direction of a winding center axis. The inductor wiring line is connected to a first external electrode at a first end, and connected to a second external electrode at a second end. The component body includes: a first inclined surface connected to a first end of the mounting surface on a first side in a length direction and inclined toward the top surface as separating from the first end; and a second inclined surface connected to a second end of the mounting surface on a second side in the length direction and inclined toward the top surface as separating from the second end. The winding center axis extends in a direction parallel to the mounting surface and perpendicular to the length direction.