An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

A ceramic electronic component that includes an electronic component body having a superficial base ceramic layer; a surface electrode on a surface of the electronic component body, a peripheral section of the surface electrode having an opening therein; and a covering ceramic layer covering the peripheral section of the surface electrode and the opening therein.

Embodiments of the invention include LED lighting systems and methods. For example, in some embodiments, an LED lighting system is included. The LED lighting system can include a flexible layered circuit structure that can include a top thermally conductive layer, a middle electrically insulating layer, a bottom thermally conductive layer, and a plurality of light emitting diodes mounted on the top layer. The LED lighting system can further include a housing substrate and a mounting structure. The mounting structure can be configured to suspend the layered circuit structure above the housing substrate with an air gap disposed in between the bottom thermally conductive layer of the flexible layered circuit structure and the housing substrate. The distance between the layered circuit structure and the support layer can be at least about 0.5 mm. Other embodiments are also included herein.

A printed circuit board, on which at least one light emitting diode including at least two electrodes is mounted, includes a base member, an insulating layer disposed on the base member, a plurality of conductive pads disposed on the insulating layer and electrically connected to the light emitting diode, a plurality of via holes formed through at least one conductive pad of the plurality of conductive pads and at least a portion of each insulating layer, and filling members disposed in the plurality of via holes to electrically connect the base member to the at least one conductive pad, A distance between the plurality of via holes is ‘n’ times greater than a depth of at least one via hole of the plurality of via holes, in which ‘n’ is a positive integer greater than ‘1’ and less than ‘10’.

An optical module includes: an optical sub-assembly; and a flexible substrate including an insulating film, an interconnection pattern, and a spacer layer, the flexible substrate being connected to the optical sub-assembly. The insulating film has some projections, the projections protruding from a basic area in a first direction, the projections being arranged in a second direction perpendicular to the first direction, the insulating film having a flat shape with a recess between an adjacent pair of the projections. The interconnection pattern includes some pads in the basic area on a first surface of the insulating film, the pads being arranged in the second direction. The pads include some first pads adjacent to the respective projections, the pads including at least one second pad adjacent to the recess. The spacer layer is on the first surface and at each of the protrusions.

A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; and a cavity formed in the first and second insulating layers; wherein the cavity includes a first portion formed in the second insulating layer; and a second portion formed in the first insulating layer; wherein the first portion has a first cross-sectional shape, and wherein the second part has a second cross-sectional shape different from the first cross-sectional shape.

A circuit board is disclosed, including a circuit board body and at least one via apparatus provided on the circuit board body. The via apparatus includes a via (101) formed on the circuit board body, a via pad (201) surrounding the via and separately provided from the via, and an electrical conductor (301) electrically connecting the via pad (201) with the via (101).

A component carrier has a laminated stack including at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a front-end chip on and/or in the stack and extending at least up to a main surface of the stack, an antenna interface on an opposing other main surface of the stack, and an impedance matching circuitry in the stack and arranged vertically between the front-end chip and the antenna interface.

A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.

A set of features for a product is identified. It is determined that preventing an electrical connection at a ball-grid-array location on a ball-grid-array assembly of the product would result in the set of features. The ball-grid-array location is established as a target BGA location based on that determination. Suction is applied to a via at the target BGA location during reflow of the ball-grid-array assembly. With that application of suction, a solder ball at the target BGA location is drawn into the via.