A method of manufacturing a component carrier includes laser drilling a blind hole in a layer stack, and subsequently extending the blind hole to a through hole by etching. A component carrier includes an electrically insulating layer structure, an electrically conductive layer structure directly on an electrically insulating layer structure, and a tapering through hole extending through the electrically conductive layer structure and through the electrically insulating layer structure with a lateral overhang of the electrically conductive layer structure beyond the electrically insulating layer structure at the tapering through hole of not more than 20% of a maximum diameter of the tapering through hole.

An all-directions embedded module includes a substrate layer, many first embedded pads, many second embedded pads, and many side wall circuits. The substrate layer comprises a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connected to the first surface and the second surface. The first embedded pads is formed on the first surface. The second embedded pads is formed on the second surface. The side wall circuits embedded in the substrate layer and exposed from the side surfaces. The all-directions embedded module further includes a plurality of first connecting circuits formed on the first surface and a plurality of second connecting circuits formed on the second surface. The first embedded pads is connected to the side wall circuits by the first connecting circuits. The second embedded pads is connected to the side wall circuits by the second connecting circuits.

A current path is provided through an interposer to ground a grounding pattern associated with a transmission line, by exploiting an interposer substrate that has a high-resistivity portion at a first surface and a low-resistivity portion extending from the high-resistivity portion to a second surface of the interposer. Moreover, a set of blind via-holes comprising electrically-conductive material extend from the first surface of the interposer substrate through the high-resistivity portion and into the low-resistivity portion. Top-to-bottom connection can be made using the conductive material in the blind vias and using the low-resistivity portion of the substrate, while the high-resistivity portion of the substrate impedes current leakage from the transmission line to the second surface of the substrate. The number and dimensions of the blind via-holes control the impedance of the grounding pattern relative to the transmission line's characteristic impedance.

A method for forming a circuit board having a dielectric core, a foil top surface, and a thin foil bottom surface with a removable foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling utilizes a sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step, which provide dot vias of fine linewidth and resolution.

A method is disclosed for mounting and cooling a circuit component having aplurality of contacts. The method comprises mounting the circuit component on a rigid substrate of a thermally conductive and electrically insulating material with a circuit board arranged between the circuit component and the substrate. The circuit board, which has a flexible base and carries conductive traces that terminate in contact pads, is secured to the rigid substrate with at least some of the contact pads on the circuit board disposed on the side of the circuit board facing the rigid substrate, at least some of the latter contact pads being bonded to the substrate. To establish both an electrical and a thermal connection between the contacts of the circuit component and the contact pads bonded to the substrate, blind holes are formed in the flexible base of the circuit board, each hole terminating at a respective one of the contact pads bonded to the substrate. The side of the contact pads exposed by the holes is plated to form conductive vias that fill the holes and that are soldered to the contacts of the circuit component.

A multilayer substrate includes a resin multilayer body including, in a lamination direction, first and second laminate portions respectively including first and second thermoplastic resin layers, and a first interlayer connection conductor extending through the first thermoplastic resin layer. A storage elastic modulus of the first thermoplastic resin layer is lower than that of the second thermoplastic resin layer at a measurement temperature equal to or higher than a minimum melting point among melting points of metallic elements included in the first interlayer connection conductors and equal to or lower than melting points of the first thermoplastic resin layer and the second thermoplastic resin layer.

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a hole in the stack having a first hole portion covered with metal and having a second hole portion not covered with metal, wherein the second hole portion is defined by an anti-plating dielectric structure and an electroless plateable separation barrier.

A printed wiring board includes a base layer having insulating properties, a first conductive layer directly or indirectly stacked on the base layer front surface, and including a copper foil, a second conductive layer directly or indirectly stacked on the base layer back surface, and including a copper foil, a stacked body for a via hole, the stacked body being stacked on an inner periphery and a bottom of a connection hole that extends through the first conductive layer and the base layer in a thickness direction, and being configured to electrically connect the first conductive layer and the second conductive layer to each other, and having an electroless copper plating layer. Each copper foil contains a copper crystal grain oriented in a plane orientation, and an average crystal grain size of copper of each copper foil is 10 μm or greater, the electroless copper plating layer includes palladium.

A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

Provided are flexible hybrid interconnect circuits and methods of forming thereof. A flexible hybrid interconnect circuit comprises multiple conductive layers, stacked and spaced apart along the thickness of the circuit. Each conductive layer comprises one or more conductive elements, one of which is operable as a high frequency (HF) signal line. Other conductive elements, in the same and other conductive layers, form an electromagnetic shield around the HF signal line. Some conductive elements in the same circuit are used for electrical power transmission. All conductive elements are supported by one or more inner dielectric layers and enclosed by outer dielectric layers. The overall stack is thin and flexible and may be conformally attached to a non-planar surface. Each conductive layer may be formed by patterning the same metallic sheet. Multiple pattern sheets are laminated together with inner and outer dielectric layers to form a flexible hybrid interconnect circuit.