Patent classifications
H05K2201/09509
Method for producing a printed circuit board
A method for producing a printed circuit board is disclosed, In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.
METHOD FOR MANUFACTURING CIRCUIT BOARD
A circuit board includes a substrate, a first inner circuit layer, a second inner circuit layer, a first insulating layer, a first optical fiber extending along a first direction, an optical component, an electrical component, a transparent insulating layer, a first inclined surface, a first reflective layer, a second inclined surface, a second reflective layer, and a second optical fiber extending along a second direction.
FLEXIBLE CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a flexible circuit board includes providing a first laminated structure, the first laminated structure including two first wiring boards, a first adhesive layer sandwiched between the two first wiring boards, and a first conductive structure. The first conductive structure penetrates the two first wiring boards and the first adhesive layer and electrically connects the two first wiring boards. The first adhesive layer defines a first opening, the first opening includes a first edge away from the first conductive structure. The first laminated structure is cut along the first edge and then the two first wiring boards are unfolded. A flexible circuit board manufactured by such method is also disclosed.
PRINTED WIRING BOARD
A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, and a via conductor formed in the insulating layer such that the via conductor is connecting the first and second conductor layers. The insulating layer has opening exposing portion of the first conductor layer such that the via conductor is formed in the opening, the second conductor layer and via conductor are formed such that the second conductor layer and via conductor include a seed layer and an electrolytic plating layer on the seed layer, and the insulating layer includes resin and inorganic particles dispersed in the resin such that the particles include first particles forming inner wall surface in the opening and second particles embedded in the insulating layer and the first particles have shapes different from shapes of the second particles.
Solder-Free Component Carrier Connection Using an Elastic Element and Method
An arrangement is illustrated and described. The arrangement includes a component carrier including ia) a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and ib) at least one elastic element attached to the stack and configured to reversibly connect the component carrier with a further component carrier by elastically deforming the at least one elastic element and essentially not deforming the stack and the further component carrier; ii) the further component carrier connected with the component carrier by the at least one elastic element, wherein the further component carrier includes: iia) a further recess configured such that the component carrier is at least partially placeable into the further recess; iii) the component carrier is a smaller unit than the further component carrier, and iv) the component carrier is at least partially placed into the further recess.
Semiconductor Chip Module
A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal may receive the first signal from the buffer at the same time. The first connection terminal may be closer to the buffer as compared with the second connection terminal. The third connection terminal may be closer to the buffer as compared with the fourth connection terminal.
Printed circuit board and insulating film used therein
A printed circuit board includes: an insulating layer including an insulating resin and first fillers dispersed in the insulating resin; and a wiring layer disposed on the insulating layer. The first filler includes a core, and a shell coated on a surface of the core, and the shell has a dielectric constant higher than that of the core.
Carrier with Downsized Through-Via
In an embodiment a carrier includes a base substrate, at least one insulating layer, at least one inner wiring layer, at least one outer wiring layer and at least one through-via in the insulating layer extending through the insulating layer, wherein the base substrate and the insulating layer are formed from different materials, wherein the base substrate is formed for mechanically stabilizing the carrier and supports the insulating layer, wherein the inner wiring layer is arranged in a vertical direction at least in places between the base substrate and the insulating layer, wherein the outer wiring layer is spatially separated from the inner wiring layer at least in places by the insulating layer, and wherein the through-via electrically conductively connects the inner wiring layer to the outer wiring layer and has a lateral cross-section having a maximum lateral extent of at most 100 μm.
WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE
A wiring substrate includes a first insulating layer, a first conductor layer formed on the first insulating layer, a second insulating layer formed on the first conductor layer, a second conductor layer formed on the second insulating layer, and a via conductor formed in the second insulating layer such that the via conductor is connecting the first and second conductor layers. The second insulating layer has a via hole in which the via conductor is formed, and the via conductor includes a first plating film and a second plating film such that the first plating film has a bottom portion formed at bottom of the via hole and a side portion formed on side of the via hole and separated from the bottom portion by gap and that the second plating film is covering the gap of the first plating film and at least part of the first plating film.
Microelectronic device and circuit board thereof
A microelectronic device includes an accommodating housing, a circuit board, an electronic component, and a conducting wire. The accommodating housing has an accommodating space therein. The circuit board is disposed within the accommodating space, and has a first and a second end surface disposed opposite to each other. The first end surface includes a first conductive contact, and a lateral side of the circuit board includes a receiving hole being a half-open hole extending from the second end surface. A second conductive contact is disposed on the surface of the receiving hole and electrically connected to the first conductive contact via an internal power layer of the circuit board. The electronic component is disposed on the first end surface and electrically connected to the first conductive contact. One end of the conducting wire is disposed in the receiving hole and electrically connected to the second conductive contact.