The present disclosure provides a circuit board. The circuit board may include a number of stacked core boards each having a top surface. At least part core boards of the number of stacked core boards may include circuit layers at top surfaces thereof. A groove may be defined through the at least part core boards. A conductive material may be received in the groove configured to couple to the circuit layers of at least two core boards. A cross section of the groove may include a length in a first direction and a length in a second direction, and the length in the first direction may be greater than the length in the second direction. Electroplating solution may capable of contacting any portions of the groove to electroplate, to form the conductive material.

A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

Provided is a method of measuring eccentricity of a blind via hole formed in a printed circuit board including an inner-layer board and an outer-layer board that are bonded by thermocompression bonding. The method includes acquiring, by a microscope camera, an image by photographing a marker which is formed on a surface of the outer-layer board and a blind via hole which is exposed upward through a marker hole formed in a center of the marker with a microscope camera, and measuring, by computing equipment connected to the microscope camera, eccentricity indicating a separation distance and a separation direction from central coordinates of the marker hole to central coordinates of the blind via hole using a distance between an end point of the marker hole and an end point of the blind via hole which are included in the image.

The present disclosure provides a multilayer wiring structure, including a plurality of dielectric layers, a plurality of conductive wiring layers interleaved with the plurality of dielectric layers, wherein the plurality of conductive wiring layers includes copper-phosphorous alloys (such as Cu.sub.3P).

A method is disclosed for mounting and cooling a circuit component having a plurality of contacts. The method comprises mounting the circuit component on a rigid substrate of a thermally conductive material having and electrically insulating regions with a circuit board arranged between the circuit component and the substrate. The circuit board, which carries conductive traces that terminate in contact pads, is secured to the substrate with at least some of the contact pads on the circuit board disposed on the side of the board facing the substrate, some of which being bonded to the substrate. To establish both an electrical and a thermal connection between the contacts of the circuit component and the contact pads bonded to the substrate, blind holes are formed in the base of the circuit board, each hole terminating at a respective one of the contact pads bonded to the substrate.

An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.

The disclosure provides a circuit board that includes: a carrier element having a number of circuit board layers; a number of electronic components; a number of thermal interfaces; and a number of electrical interfaces. The electronic components are arranged directly on at least one of the surface sides on the carrier element. The opposite surface side of the carrier element is of potential-free design. Additionally, the circuit board with the electronic components is overlaid by a covering material in such a way that the electronic components are mechanically stabilized and the thermal and/or electrical interfaces are free of the covering material.

An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

A method for producing a printed circuit board structure comprising at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layer are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component.

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component including a terminal made of a first electrically conductive material and being embedded in the stack, a recess in the stack exposing at least a part of the terminal, an interface structure on the at least partially exposed terminal and an electrically conductive structure on the interface structure made of a second electrically conductive material.