Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

A circuit board having excellent reliability of connection between layers while being capable of achieving a compact and low-profile electronic device. In the circuit board has an LC circuit built therein with the use of a glass core having a through hole, a conductor layer formed in the through hole is connected to a wiring pattern formed on one surface of the glass core, and connected to a wiring pattern formed on the other surface of the glass core, with the conduction layer projected from the surface of the glass core. Thus, the area of contact between the conduction layer and the through hole is increased, thus making it possible to prevent the reliability of connection between layers in the through hole from being decreased, even when the glass core is reduced in thickness for achieving a low-profile device.

A connection method for a chip and a circuit board includes: placing the circuit board on the chip, the circuit board having a first surface in contact with the chip having a plurality of contacts, and the circuit board having a plurality of through holes aligned with the plurality of contacts respectively; placing a mask on a second surface of the circuit board, the mask having a plurality of openings aligned with the plurality of through holes respectively; covering a surface of the mask with a conductive adhesive to fill the plurality of through holes with the conductive adhesive; and keeping portions of the conductive adhesive that are respectively in the plurality of through holes to be spaced apart from each other. The portions of the conductive adhesive that fill the plurality of through holes remain to provide an electrical connection between the circuit board and the chip.

A printed circuit board and/or an electronic device including the same are provided. The printed circuit board and/or an electronic device includes at least one insulation layer including a first rigid region and a flexible region extending from the first rigid region, at least one first circuit pattern disposed on one surface of the at least one insulation layer to at least partially transverse the flexible region from the first rigid region, and at least one conductive pad formed at least partially on a surface of the first circuit pattern in the first rigid region, wherein the flexible region may be configured to flexibly deform more than the first rigid region.

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

Methods and apparatus relating to phase heterogeneous interconnects for crosstalk reduction are described. In one embodiment, an interconnect includes a plurality of links. A first set of links from the plurality of links communicates signals and a second set of links from the plurality of links provides a return path. The interconnect also includes one or more links from the first set of links that include one or more structures with a larger diameter than a minimum diameter of the one or more links. The larger diameter modifies an inductance or capacitance of the one or more links to provide a heterogenous phase delay amongst the plurality of links. Other embodiments are also claimed and disclosed.

A component carrier having a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure; an opening located at least partially in the stack; and a fill material which is located within the opening. The fill material is a photosensitive material, wherein at least a part of the photosensitive material has undergone a hardening treatment with electromagnetic radiation. A method for manufacturing such a component carrier is further described.

A flexible printed circuit for bridging is provided. The flexible printed circuit has at least one via, at least one overflow groove is provided at a first distance from an edge of the via, and the overflow groove is provided in a cover layer on a side of a soldering surface of the flexible printed circuit.

A multilayer substrate and a manufacturing method thereof are disclosed. The multilayer substrate includes two or more dielectric layers laminated in sequence; a public line disposed at a top or bottom dielectric layer of the two or more dielectric layers; and two or more first through hole pillars respectively each embedded in a respective one of the dielectric layers, and the first through hole pillars are connected in cascade and then connected with the public line.

An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.