Forming, in a printed-wiring board, a via sufficiently filled without residual smear, for use in an insulating layer and the size of the via to be formed. A via of a printed-wiring board comprises a first filling portion which fills at least a center portion of a hole, and a second filling portion which fills a region of the hole that is not filled with the first filling portion. An interface which exists between the second and first filling portions, or an interface which exists between the second filling portion and an insulating layer and the first filling portion has the shape of a truncated cone comprising a tapered surface which is inclined to become thinner from a first surface toward a second surface, and an upper base surface which is positioned in parallel to the second surface and closer to the first surface than to the second surface.

The disclosure provides an electronic device. The electronic device includes a plurality of units. Each of the units includes an integrated substrate. The integrated substrate includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer. The first dielectric layer has a first side and a second side opposite to the first side. The first conductive layer is disposed on the first side. The second dielectric layer has a third side facing the second side and a fourth side opposite to the third side. The second conductive layer is disposed on the fourth side. A loss tangent of at least one of the first dielectric layer and the second dielectric layer is less than or equal to 0.1 and greater than 0. The electronic device of an embodiment of the disclosure may improve product yield.

Embodiments disclosed herein comprise package substrates and methods of forming package substrates. In an embodiment, a package substrate comprises a core substrate. A hole is disposed into the core substrate, and a via is disposed in the hole. In an embodiment, the via completely fills the hole. In an embodiment, a method of forming a package substrate comprises exposing a region of a core substrate with a laser. In an embodiment, the laser changes the morphology of the exposed region. The method may further comprise etching the core substrate, where the exposed region etches at a faster rate than the remainder of the core substrate to form a hole in the core substrate. The method may further comprise disposing a via in the hole.

A component carrier assembly includes a first component carrier having a first electrically insulating layer structure and a via in the first electrically insulating layer structure, where the via is at least partially filled with electrically conductive material and where an upper part of the via extends beyond an outer main surface of the first component carrier; and a second component carrier having a second electrically insulating layer structure, and an electrically conductive adhesive material that is at least partially embedded in the second electrically insulating layer structure. The first component carrier and the second component carrier are interconnected and the upper part of the via at least partially penetrates into the electrically conductive adhesive material.

A wiring circuit board includes a porous insulating layer, and a first conductive layer sequentially toward one side in the thickness direction. The first conductive layer includes a first signal wire and first ground wires. Each of the first ground wires is thicker than the first signal wire.

An electronic device, comprising: a first functional board, a second functional board, and a connector main body, wherein the connector main body is a PCB, wherein a plurality of via holes are formed in the PCB, wherein soldering pads are arranged in the via holes, and wherein the soldering pads are used for communicating the first functional board and second functional board, wherein the PCB is provided with a space for accommodating elements on the first and second functional boards, wherein the soldering pads on both sides of the connector are respectively connected with the soldering pad of the first functional board and the soldering pad of the second functional board.

A low passive intermodulation (PIM) coaxial-to-printed circuit board (PCB) interface and method of constructing the same. According to one aspect, a coaxial-to-PCB interface couples signals between an electrical conductor trace in the PCB and an inner conductor of a coaxial structure having an insulator surrounded by an outer conductor. A metallic cylinder is inserted over the outer conductor of the coaxial structure and positioning the coaxial structure with respect to the PCB so that the outer conductor and insulator of the coaxial structure lie below a lower surface of the PCB. The inner conductor of the coaxial structure is inserted into a via extending from the lower surface of the PCB to an upper surface of the PCB. Solder is deposited in the via to provide an electrically conductive path between the electrical conductor trace of the PCB and the inner conductor of the coaxial structure.

A printed circuit board according to an embodiment includes an insulating layer; and a via portion disposed on the insulating layer; wherein the via portion includes: a first pad disposed under the insulating layer; a second pad disposed on the insulating layer; and a via part disposed between the first and second pads in the insulating layer; and wherein a width of the first pad is less than or equal to a width of a lower surface of the via part.

A method of producing a multilayer printed circuit board includes a metallic conductor structure including providing a base substrate including a film or plate and having first and second substrate sides, which base substrate at least partly consists of an electrically non-conductive organic polymer material and wherein the first substrate side is covered with a cover metal layer, partially removing the cover metal layer while subdividing the first substrate side into at least one first partial area, in which the first substrate side is free of the cover metal layer, and into at least one second partial area, in which the first substrate side is covered with the cover metal layer, and causing a plasma to act on the first substrate side with the aid of which plasma the polymer material is removed in the at least one first partial area while forming at least one trench.

A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.