Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

A printed circuit board including: a first insulating layer; a first wiring layer disposed on an upper surface of the first insulating layer, and including a first wiring portion and a second wiring portion; and a second insulating layer disposed on the upper surface of the first insulating layer, having a cavity exposing an upper surface of the second wiring portion, and including a first insulating portion covering the first wiring portion and a second insulating portion whose upper surface is exposed from the cavity, wherein one or more gaps are provided between the second wiring portion and the second insulating portion.

A wiring substrate includes: a base material; a first through-hole and a second through-hole that are formed in the base material; magnetic material that is filled in the first through-hole; a third through-hole that is formed in the magnetic material; a first plating film that covers an inner wall surface of the third through-hole; and a second plating film that covers an inner wall surface of the second through-hole and the first plating film. The first plating film includes a first electroless plating film that is in contact with the inner wall surface of the third through-hole, and a first electrolytic plating film that is laminated on the first electroless plating film.

Provided are flexible hybrid interconnect circuits and methods of forming thereof. A flexible hybrid interconnect circuit comprises multiple conductive layers, stacked and spaced apart along the thickness of the circuit. Each conductive layer comprises one or more conductive elements, one of which is operable as a high frequency (HF) signal line. Other conductive elements, in the same and other conductive layers, form an electromagnetic shield around the HF signal line. Some conductive elements in the same circuit are used for electrical power transmission. All conductive elements are supported by one or more inner dielectric layers and enclosed by outer dielectric layers. The overall stack is thin and flexible and may be conformally attached to a non-planar surface. Each conductive layer may be formed by patterning the same metallic sheet. Multiple pattern sheets are laminated together with inner and outer dielectric layers to form a flexible hybrid interconnect circuit.

A planar multi-layer assembly method fabricates a dual frequency, dual polarization phased-array antenna. A plurality of vias make up an array of double-walled wells which are connected to a ground plane. A shorted annular ring patch antenna (SARPA) is deposited at the top of each double-walled well. Fabricated coaxially and parallel to each SARPA, is an array of circular patch antennas (CPA). The inner wall of each double-walled well improves isolation of the CPA signals from the SARPA signals. Each SARPA of the array is connected to a pair of first frequency band signal vias and the CPA is coupled to a pair of second frequency band signal vias. Within each frequency band, a plurality of signal phases enable steerable polarized antenna beams.

An electronic device includes a supporting board, an electrical board and electronic units. The supporting board includes a circuit layer. The electrical board has a board body, through holes through the board body, an electrical layer on the board body, and primary conductive elements respectively in the through holes. The board body has opposite first and second surfaces. The through holes communicate with the first surface and the second surface. The primary conductive elements electrically connect the electrical layer to the circuit layer. The electronic units are arranged on the first surface. Each electronic unit partially overlaps with one corresponding through hole in a projection direction of the electrical board. Each electronic unit has an electronic component and a secondary conductive element electrically connecting the electronic component to the electrical layer. The secondary conductive elements and the primary conductive elements are arranged in dislocation in the projection direction.

A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.

A multilayered substrate includes unit substrates laminated in a direction of thickness thereof, and the unit substrates include a photosensitive insulating layer, a conductive pattern disposed in the photosensitive insulating layer, and a bump penetrating into the photosensitive insulating layer and providing an interlayer connection to the conductive pattern.

A circuit board includes a plurality of first insulating base materials and a plurality of second insulating base materials that are alternately laminated, a first metal layer being formed into a pattern shape on a first surface of the first insulating base material, and a second metal layer being formed into a pattern shape on a second surface of the first insulating base material. The first metal layer is formed into a trapezoidal shape that is large in diameter on a first surface side of the first insulating base material. The second metal layer is formed into a trapezoidal shape that is large in diameter on a second surface side of the first insulating base material. The first metal layers and the second metal layers are laminated in such a manner that the trapezoidal shapes are alternately oriented.

A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.