A method for manufacturing a component carrier includes covering a dielectric layer structure by a metal foil, forming an electroless metal layer on the metal foil, and forming a multi-stage electroplating structure on the electroless metal layer. A component carrier made by the method is further described.

A method for producing a flexible printed circuit board according to an embodiment of the present invention includes a through-hole formation step of preparing a base material including a base film having insulating properties and flexibility and a pair of metal films stacked on both surface sides of the base film, and forming a through-hole in the metal film on a front surface side of the base material and the base film; a filling step of stacking, by electroplating on a front surface of the base material, stacking a conductive material on a surface of the metal film on the front surface side to form a conductive material layer and to fill the through-hole with the conductive material; and a removal step of removing, by etching the front surface of the base material, a surface layer of the conductive material layer stacked on the surface of the metal film on the front surface side and a surface layer of the conductive material filling the through-hole.

A through wiring substrate comprises a substrate having a pair of principal surfaces and a through hole penetrating between the pair of principal surfaces, the pair of principal surfaces and an inner surface of the through hole being electrically insulative; a through electrode provided on the inner surface of the through hole; a first wiring layer provided on one of the principal surfaces and connected to the through electrode; a second wiring layer provided on the other of the principal surfaces and connected to the through electrode; an underlying metal layer provided between the one of the principal surfaces and the first wiring layer; and catalyst metal particles existing between the underlying metal layer and the first wiring layer and between the through electrode and the inner surface of the through hole.

A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.

A wiring substrate includes a first conductor pattern, a second conductor pattern, an insulating layer interposed between the first and second patterns and having a through hole, and a plating conductor integrally formed with the second pattern and filling the through hole in the insulating layer such that the plating conductor is in contact with the first pattern. The through hole has an expansion part such that an opening width of the through hole on the first pattern side is widened, and the plating conductor includes a first plating film directly formed on inner wall of the through hole and a second plating film formed on the first plating film such that the minimum thickness of the first plating film in the expansion part is in the range of 55% to 95% of the minimum thickness of the first plating film in the through hole other than the expansion part.

A multilayer wiring board includes a first insulating layer, a second insulating layer stacked on the first insulating layer, a via conductor inside each of the first insulating layer and the second insulating layer, and a conductive bonding layer that bonds the via conductors to each other. The first insulating layer is directly bonded to the second insulating layer, and a relationship a.sub.1>b.sub.1 is satisfied, where a.sub.1 is a maximum diameter of the bonding layer and b.sub.1 is a maximum diameter of the via conductor at an interface with the bonding layer.

A multilayer substrate includes a plurality of insulator layers laminated, a column conductor extending through two or more insulator layers among the plurality of insulator layers. The column conductor includes a first via conductor extending through a first insulator layer and a second via conductor extending through a second insulator layer adjacent to the first insulator layer. Each of the first via conductor and the second via conductor has a tapered shape in which a cross section decreases from one end portion to the other end portion in the lamination direction of the plurality of insulator layers. The first via conductor and the second via conductor are directly bonded to each other at large diameter portions that are end portions with a large cross section or small diameter portions that are end portions with a small cross section.

An apparatus comprising a stack of printed circuit board (PCB) layers having a primary longitudinal structure forming a radio frequency (RE) via including a principal tuning section (223) and a constant longitudinal structure (227) along a conductive column support (255) journaled through the layers in the via. The principal section (221) comprising a first tuning sub-assembly (229 A) in a first portion of the RE via above the longitudinal structure (227) and at an entrance of the primary longitudinal structure (221) and comprising a first set of pad, anti-pad pairs (445, 545, 645) tuned to receive an RE band. A second principal tuning sub-assembly (229B) in a second portion of the via below the longitudinal structure (227) and at an exit of the primary longitudinal structure and comprising a second set of pad, anti-pad pairs (445, 545, 645) tuned to receive the band and mirroring the first set of pairs.

A method for producing a package substrate for mounting a semiconductor device includes:

forming a first substrate by forming a laminate in which a first metal layer that has a thickness of 1 μm to 70 μm and that is peelable from a core resin layer, a first insulating resin layer, and a second metal layer are arranged on both sides of the core resin layer having a thickness of 1 μm to 80 μm, and heating and pressurizing the laminate simultaneously;

forming a pattern on the second metal layer;

forming a second substrate by heating and pressurizing a laminate formed by arranging a second insulating resin layer and a third metal layer on a surface of the second metal layer; and

peeling, from the core resin layer, a third substrate including the first metal and insulating resin layers, the second metal and insulating layers, and the third metal layer.

A wiring body includes: a core insulating base material having a first main surface and a second main surface; a signal line and a first power supply line provided on the first main surface; a second power supply line provided on the second main surface and electrically connected to the first power supply line; a first dielectric layer laminated on the first main surface so as to embed the signal line and the first power supply line; a first ground layer provided on the first dielectric layer; a second dielectric layer laminated on the second main surface so as to embed the second power supply line; and a second ground layer provided on the second dielectric layer and sandwiching at least the signal line together with the first ground layer.