A printed circuit board includes a first insulating layer; a protective filler layer disposed on one surface of the first insulating layer; a first wiring layer disposed on the one surface of the first insulating layer and having a pad protruding with respect to the protective filler layer; a first via passing through the first insulating layer and contacting the pad; and a second insulating layer disposed on the first wiring layer and the protective filler layer, and having a cavity exposing the pad and at least a portion of the protective filler layer, respectively.

A multilayer ceramic capacitor includes a multilayer body including dielectric layers, first inner electrodes, and second inner electrodes stacked on one another, a first outer electrode electrically connected to the first inner electrodes, and a second outer electrode electrically connected to the second inner electrodes. The multilayer body includes first and second side surfaces respectively including first and second recesses where a midsection of each of the first and second side surfaces in a length direction is recessed inward in a width direction. When the multilayer ceramic capacitor is viewed in a stacking direction, a dimension of each of the first and second recesses in the length direction is smaller on an inner side than on an outer side in the width direction.

A substrate layered structure including a first circuit board; a second circuit board overlapping the first circuit board; and interposer blocks interposed between the first circuit board and the second circuit board and spaced apart from each other. Further, each corresponding interposer block includes a dielectric block body; a plurality of signal via holes passing through the dielectric block body and transferring signals between the first circuit board and the second circuit board; and a plurality of signal pads arranged at first ends of the signal via holes and connected to the first circuit board and arranged at second ends of the signal via holes and connected to the second circuit board.

Disclosed is a portable communication device including a housing, a first printed circuit board (PCB) disposed in the housing, a wireless communication circuit mounted on the first PCB, and a second PCB including a connection part connected with the first PCB, a first PCB portion extended from the connection part and having greater flexibility than the connection part, a second PCB portion extended from the first PCB portion and having less flexibility than the first PCB portion, a third PCB portion extended from the second PCB portion and having greater flexibility than the second PCB portion, a fourth PCB portion extended from the third PCB portion and having less flexibility than the first PCB portion, a signal line extended to the connection part along the first, second, third, and fourth PCB portions, and vias arranged in at least a partial area of the second PCB portion or the fourth PCB portion, wherein a portion of the signal line is located between some of the vias.

This anisotropic conductive sheet includes: an insulating layer having a first surface and a second surface; and a plurality of conductive paths which are disposed so as to extend in the thickness direction inside the insulating layer and which are respectively exposed to the outside of the first surface and the second surface. The circumferential surface of the conductive paths includes a region where the surface area ratio represented by equation (1) is at least 1.04. Equation (1): surface area ratio = surface area / area

A wiring board includes: an insulating member having a first upper surface, and a second upper surface located higher than the first upper surface; and a first wiring layer located on the first upper surface. The first upper surface has a wiring region that does not overlap with the second upper surface in a top view, and that is located in an exposed region. The first wiring layer extends from the wiring region to a connecting region that is connected to the wiring region, that overlaps with the second upper surface in a top view, and that is not exposed. The first wiring layer comprises a first pad portion located in the wiring region, and a first pattern portion located in the connecting region.

Examples are disclosed related to forming solder joints between printed circuits by using radiant heat. One example provides a method of manufacturing an electronic device, the method comprising aligning a contact of a first printed circuit with a via of a second printed circuit. The method further comprises applying radiant heat via an infrared light source to a second surface of the second printed circuit, the radiant heat incident on the via to cause the via to conduct heat to solder located at an interface of the contact and the via, and after heating the solder to reflow, cooling the solder, thereby forming a solder joint between the contact of the first printed circuit and the via of the second printed circuit.

An electronic device including a housing; a printed circuit board (PCB) in the housing, wherein the PCB includes a plurality of layers with one or more conductive and insulation layers; a first electrical component formed as at least a part of or in the housing; a second electrical component above or near the PCB in the housing, wherein the first and second electrical components are separated; and at least one electrical path extending from the first electrical component to the second electrical component, wherein at least a portion of the electrical path runs on or inside the PCB, wherein the PCB includes a region including a pattern of conductive vias, wherein each of the vias extends through at least part of the plurality of layers to contact at least one of the one or more conductive layers, and wherein the electrical path runs through the region without contacting the vias.

Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

A galvanic isolator includes a multi-layer printed circuit board (PCB) including a dielectric material having a top side and a bottom side. An RF transmission line is embedded within the PCB including a plurality of conductor traces spaced apart from one another to include a plurality of gaps (G1 and G2) in a path of the RF transmission line to provide an inline distributed capacitor that together with an impedance of the RF transmission line forms a bandpass (BP) filter. A top metal layer is on the top side and a bottom metal layer on the bottom side connected to one another by a plurality of metal filled vias on respective sides of the RF transmission line. The top metal layer and bottom metal layer each also include at least one gap.