A semiconductor device comprises a printed circuit board (PCB), a plurality of vias, and a communication buss. The PCB comprises a plurality of layers. The first layer of the plurality of layers is configured to receive a first integrated circuit (IC) device and a second IC device. The plurality of vias is disposed within the plurality of layers. A first via of the plurality of vias is configured to be connected to the first IC device, and a second via of the plurality of vias is configured to be connected to the second IC device. The communication bus comprises a first trace connected to the first via. The communication device further comprises a second trace disposed on a third layer of the plurality of layers and connected to the first via. The first trace is disposed on a layer of the plurality of layers other than the second layer.

A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.

A multilayer printed circuit having a control circuit including n vias that are connected in series between a first and a second electrical terminal so that an applied electric current passes at least partially through each one of the n vias. The control circuit includes track portions in each one of the layers, each one of the n vias connecting a track portion of one layer to a track portion of another layer. The control circuit includes a measurement device for measuring a potential difference across its terminals, storage for storing a threshold value and a comparator for comparing the potential difference with the threshold value so as to validate the printed circuit when the potential difference is lower than the threshold value.

A method for manufacturing a light-emitting module includes a step of providing a bonded board including a board including, on a first surface, a circuit pattern and wiring pads that are continuous with the circuit pattern and each have bottomed holes and light-emitting segments connected on a second surface of the board with an adhesive sheet interposed therebetween and including an array of light-emitting devices; a step of supplying electrically conductive paste inside the bottomed holes and on portions of the surface of the wiring pad around the bottomed holes through openings of a mask; and a step of performing thermal compression to harden the electrically conductive paste such that the thickness of the electrically conductive paste on the portions of the surface of the wiring pad is smaller than the electrically conductive paste at the timing of being disposed through the openings of the mask.

A circuit board includes an insulating material; and a heat-transfer structure comprising a plurality of heat-dissipating members and inserted in the insulating material, wherein the plurality of heat-dissipating members each includes a metal wire; and an insulating part disposed on an outer circumferential surface of the metal wire excluding a top surface and a bottom surface of the metal wire.

A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones. The conductive pattern is electrically connected to a reference potential and electrically insulated from the differential transmission line pair.

A printed circuit board includes: a first electrode made of a tubular electric conductor formed on an inner wall of a first hole formed in the printed circuit board; a dielectric body disposed inside the first electrode; and a second electrode made of a tubular electric conductor formed on an inner wall of a second hole extending through the dielectric body, the second electrode having a center axis concentric with the first electrode.

A multilayer printed circuit having a control circuit including n vias that are connected in series between a first and a second electrical terminal so that an applied electric current passes at least partially through each one of the n vias. The control circuit includes track portions in each one of the layers, each one of the n vias connecting a track portion of one layer to a track portion of another layer. The control circuit includes a measurement device for measuring a potential difference across its terminals, storage for storing a threshold value and a comparator for comparing the potential difference with the threshold value so as to validate the printed circuit when the potential difference is lower than the threshold value.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

Systems and methods for applying solder to a pin. The methods comprising: disposing a given amount of solder on a non-wettable surface of a planar substrate; aligning the pin with the solder disposed on the non-wettable surface of the planar substrate; inserting the pin in the solder; and/or performing a reflow process to cause the solder to transfer from the planar substrate to the pin.