A circuit board according to an embodiment includes: a substrate including one surface and the other surface; a first circuit pattern disposed on the one surface; and a second circuit pattern disposed on the other surface, wherein at least one via is formed in the substrate, and the first circuit pattern and the second circuit pattern are wire-bonded through the via to conduct electricity.

A flexible printed circuit includes an insulating base. The insulating base includes a body portion and at least one first extension portion connected to an edge of the body portion. The first extension portion includes a via region, a bending region and a banding region that are sequentially away from the body portion. A plurality of vias are disposed in the via region. The plurality of vias include at least one first via and at least one second via, a center of an orthogonal projection of a first via on a reference plane perpendicular to a thickness direction of the insulating base is located on a first straight line parallel to a bending axis of the bending region, and a center of an orthogonal projection of a second via on the reference plane is not located on the first straight line.

A wiring board includes: a wiring-board body including a first surface and a second surface opposite to the first surface, and including at least one insulator layer; pads formed at at least one of an internal layer boundary plane and the first surface and the second surface defining a first plane; and via conductors connected to corresponding ones of the pads, and arranged in parallel to extend in a thickness direction of the wiring-board body. Each of first and second ones of the pads adjacent to each other in planar view at the first plane is connected to corresponding ones of the via conductors. The via conductors corresponding to the first pad are arranged differently from the via conductors corresponding to the second pad, in planar view.

The present invention addresses the problem of reducing a delay time difference between signals transmitted by means of a differential signal wires in a wiring board having glass cloth. A wiring board comprises: an insulating layer which includes fibers having a planar shape with translational symmetry with respect to two linearly independent, predetermined translational vectors, and a layer-like insulating material encapsulating the fibers; and through-holes formed at the starting and end points of a vector which is the sum of substantially integral multiples of the two translational vectors and which has the starting point on the planar shape.

An assembly of a printed circuit board and a card edge connector for interconnecting a memory module card is provided. The assembly includes a card edge connector and a printed circuit board for receiving the card edge connector. The card edge connector has an insulated housing and a plurality of terminals that are divided into an upper-row terminal group and a lower-row terminal group. The insulated housing has an elongated slot formed along a longitudinal direction. Each terminal group includes a first terminal, a second terminal and a third terminal. The printed circuit board has grounding via holes and plated through holes which are formed at two sides of the orthographic projection of the elongated slot. The high-frequency signal holes are separated by grounding traces or the grounding via holes, so as to provide good shielding effect for avoiding cross-talk interference.

An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.

Provided is a printed circuit board including a first semiconductor device and a second semiconductor device mounted on a printed wiring board, the printed wiring board including a first and a second differential signal wirings each formed of a pair of signal transmission lines. The pair of signal transmission lines forming the first differential signal wiring are wired to have a relative arrangement in which one signal transmission line and another signal transmission line cross with each other at least once in the first differential signal wiring in a wiring direction thereof. The pair of signal transmission lines forming the second differential signal wiring are wired to have a relative arrangement in which one signal transmission line and another signal transmission line cross with each other at least once in the second differential signal wiring in a wiring direction thereof.

The present invention provides a printed circuit board comprising: a dielectric layer (130); N pairs of differential signal vias (2) which penetrate through the dielectric layer wherein N is an integer more than one; N pairs of first strip conductors (101, 102) disposed on a first surface of the dielectric layer; a first ground conductor layer (103) disposed in the dielectric layer forming N first differential transmission lines (100) with the N pairs of first strip conductors and the dielectric layer; N pairs of second strip conductors (111,112) disposed on a second surface of the dielectric layer; a second ground conductor layer (113) disposed in the dielectric layer forming N of second differential transmission lines (110) with the N pairs of second strip conductors and the dielectric layer.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.