A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.

A circuit module includes an interposer, and the interposer includes an element body including a first surface, a first interposer terminal provided on the first surface of the element body, and connected to a first external element, a second interposer terminal provided on the first surface of the element body, and connected to a second external element, a first wiring provided in the element body, and electrically connecting the first interposer terminal and the circuit board with each other, a second wiring provided in the element body, and electrically connecting the second interposer terminal and the circuit board with each other, and a bypass wiring provided in the element body and/or on a surface of the element body, and electrically connecting the first interposer terminal and the second interposer terminal with each other.

In a multilayer ceramic capacitor, an interposer includes, on a side of a first external electrode in a length direction, a first through hole that penetrates the interposer in a stacking direction, and provides electrical conduction between a first joining electrode and a first mounting electrode. The first through hole further includes a first metal film provided on an inner wall thereof. The interposer includes, on a side of a second external electrode in the length direction, a second through hole that penetrates the interposer in the stacking direction, and provides electrical conduction between a second joining electrode and a second mounting electrode. The second through hole further includes a second metal film provided on an inner wall thereof. A first uncovered portion is provided, which is not covered by the first metal film, on a first surface of the inner wall of the first through hole, and a second uncovered portion is provided which is not covered by a second metal film on the first surface of the inner wall of the second through hole.

A transformer includes a multilayer board including insulation layers stacked in a thickness direction, a primary coil provided on at least one of the insulation layers, and a secondary coil provided on at least one of the insulation layers. The primary coil includes first sub coils electrically connected in series to each other, and second sub coils electrically connected in series to each other. Surfaces of the plurality of insulation layers constitute layer planes of the multilayer board. At least two of the first sub coils are provided on layer planes out of the layer plane different from each other. At least two of the second sub coils are provided on layer planes out of the layer planes different from each other. An average of positions of the first sub coils in the thickness direction is aligned with an average of positions of the second sub coils in the thickness direction.

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

Systems, apparatuses, and methods related to a printed circuit board (PCB) with a plurality of layers are described. An edge connector may be formed on an end of the PCB substrate and may include contact pins on an outer layer of the plurality of layers. The edge connector may also include an intra-pair coupling block disposed on one or more interior layers such that at least a portion of the intra-pair coupling block is colinear with at least one contact pin on the outer layer. The electronic device may also include at least one integrated circuit on the PCB and electrically connected to the contact pins. The intra-pair coupling component may induce coupling of signals carried by the contact pins.

An electrical contact pad for electrically contacting a connector includes first, second and third regions. The first region is connected to a trace. The second region is adjacent to the first region and has a width less than the first region. The third region is adjacent to the second region and has a width that is greater than the second region. The third region is sized to make contact with a connector. Having the width of the second region be smaller than the width of the first and third regions increases an impedance of the electrical contact pad.

Two QSFP-DD transceivers' footprints are placed on the opposite sides of a PCB board. The two footprints are aligned in a special way and the connections among the pads of the two footprints are also specially defined. Based on that, the pads of the two footprints are connected through PCB traces and VIA. Two QSFP-DD electrical connectors are soldered onto the two footprints. So the high-speed signals from two QSFP-DD transceivers are directly connected in the shortest way when the two transceivers are plugged into the two QSFP-DD connectors.

A printed circuit board, and more particularly, a printed circuit board that provides a variable inductance. A printed circuit board includes: an inductor positioned between an input terminal and an output terminal; a switch connected to the inductor; and a controller connected to the output terminal and the switch and outputting a control signal for controlling the switch to the switch, wherein the inductor is formed of a plurality of circuit patterns having different plating thicknesses and signal paths for the plurality of circuit patterns are selectively connected by operation of the switch according to the control signal.

A planar multi-layer assembly method fabricates a dual frequency, dual polarization phased-array antenna. A plurality of vias make up an array of double-walled wells which are connected to a ground plane. A shorted annular ring patch antenna (SARPA) is deposited at the top of each double-walled well. Fabricated coaxially and parallel to each SARPA, is an array of circular patch antennas (CPA). The inner wall of each double-walled well improves isolation of the CPA signals from the SARPA signals. Each SARPA of the array is connected to a pair of first frequency band signal vias and the CPA is coupled to a pair of second frequency band signal vias. Within each frequency band, a plurality of signal phases enable steerable polarized antenna beams.