A circuit board electrically connected to a chip includes a substrate and a circuit layer. A first conductive line of the circuit layer includes a main line and a branch lead connected with each other. The branch lead provided to increase lead quantity for bonding with the chip includes an extension part and a bonding part which is used for bonding a bump of the chip. During thermal compression, gaps existing between the extension part and the main line and between the bonding part and the main line can prevent solder on the main line from flowing toward the bump and overflowing from the branch lead.

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

A optical module according to the present invention includes an optical semiconductor device, a package housing the optical semiconductor device, a first pattern provided on an upper surface of the package, a second pattern provided on a side surface continuous with the upper surface of the package, a flexible substrate provided on the first pattern and extending from the upper surface to a side surface side of the package and solder joining the first pattern and the flexible substrate together, wherein the solder is spread between a portion of the flexible substrate, the portion extending from the upper surface to the side surface side of the package, and the second pattern.

An electronic device includes a printed circuit board (PCB). The PCB includes first and second grids disposed at a top surface and a bottom surface of the PCB, respectively. Each grid includes a plurality of footprint pins, and a plurality of vias extending through the PCB to the top and bottom surfaces. Each footprint pin includes a connecting end and a free end that opposes the connecting end. Each via includes a contact end located at one of grids and is in electrical contact with the connecting end of one of the footprint pins, and each via further includes a non-contact end that is located at the other of the grids and is not in electrical contact with any of the footprint pins. First and second connectors are mounted to the PCB top and bottom surfaces and connect with the footprint pins of the first and second grids.

An item may include fabric having insulating and conductive yarns or other strands of material. The conductive strands may form signal paths. Electrical components can be mounted to the fabric. Each electrical component may have an electrical device such as a semiconductor die that is mounted on an interposer substrate. The interposer may have contacts that are soldered to the conductive strands. A protective cover may encapsulate portions of the electrical component. To create a robust connection between the electrical component and the fabric, the conductive strands may be threaded through recesses in the electrical component. The recesses may be formed in the interposer or may be formed in a protective cover on the interposer. Conductive material in the recess may be used to electrically and/or mechanically connect the conductive strand to a bond pad in the recess. Thermoplastic material may be used to seal the solder joint.

Provided are a wire for use in an extendable electronic device, an extendable electronic device and preparation methods thereof. The wire is provided with a hollow region allowing extension and deformation of the wire.

A printed wiring line formed on a substrate connects two different points on the substrate which are connectable by another printed wiring line with a shape of a straight-line segment and has a shape corresponding to at least one of: 1) a shape with no linear part parallel to the straight-line segment; 2) a shape with line segments connected in series, each line segment having a shape with no linear part parallel to the straight-line segment; 3) a shape having a part parallel to the straight-line segment and a part not parallel to the straight-line segment, length of the part parallel to the straight-line segment being not more than length of the straight-line segment; and 4) a shape in which line segments are connected in series, each line segment having a shape having a part parallel to the straight-line segment and a part not parallel to the straight-line segment.

An extensible electroconductive wiring material includes a flexible electroconductive material and insulating elastic bodies and, wherein the flexible electroconductive material having an electroconductive layer has vent peripheral edge portions in which vent holes and/or vent slits are penetrated and aligned in series and/or in parallel along an energization direction of the electroconductive layer while the vent peripheral edge portions are energizably linked, and the vent peripheral edge portions is sealed and covered by the insulating elastic bodies, so as not to be exposed; and the insulating elastic bodies, have penetration slits, and/or penetration holes which penetrate therethrough while matching the vent peripheral edge portions and are smaller than the vent holes and the vent slits. The extensible electroconductive wiring module has a plurality of these extensible electroconductive wiring materials.

An electronic arrangement (100) and a method of manufacturing an electronic arrangement are provided. The electronic arrangement comprises an array of electronic components (110) arranged along a first axis, A, and a carrier (120) arranged to support the array of electronic components, wherein the carrier comprises, a first metal layer (130), a second metal layer (140), and an at least partially insulating layer (150) arranged between the first and second metal layers. The electronic arrangement further comprises a partition portion (160) arranged between two adjacently arranged electronic components for partitioning the electronic arrangement, wherein the second metal layer comprises a void (180) intersected by the second axis, wherein the void has a width (190) which extends parallel to the first axis, such that, at the second axis, the second metal layer is undercut with respect to the first metal layer, in a direction parallel to the first axis.

A substrate-integrated device includes a substrate layer with a first dielectric constant and one or more dielectric vias, the one or more dielectric vias each includes a via-hole extending through the substrate layer, and a dielectric material with a second dielectric constant contained within the via-hole. The second dielectric constant is larger than, preferably at least two times, the first dielectric constant.