A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.

An objective of the present invention is to prevent a copper foil used as a recognition mark from being stripped from a base film in a flexible printed board while preventing the recognition accuracy for the recognition mark from being reduced. A flexible printed board includes a base film; a copper foil pattern on the base film, wherein the copper foil pattern has a hollow shape with an outer circumferential section and an inner circumferential section and is configured to function as a recognition mark; a coverlay having an opening formed therein, wherein the coverlay is bonded to the base film and covers the outer circumferential section of the copper foil pattern such that an edge of the opening is positioned between the outer circumferential section and the inner circumferential section of the copper foil pattern.

Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil×8 mil cuts or indentations in the copper shape.

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

Apparatus and methods are provided for providing provide high-speed traces in inner layers of semiconductor packages or PCBs. In an exemplary embodiment, there is provided an circuit assembly that may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a pair of traces embedded therein and the first ground reference plane may have an opening corresponding to the pair of traces. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.

A wiring structure is provided, including a conductive wiring and an insulating layer. The conductive wiring is disposed on a substrate and has a top side, a bottom side and two side walls opposite to each other. The insulating layer which wraps around the conductive wiring at least through the top side and two side walls, wherein there is a gap between the insulating layer and at least one of the two side walls.

A wiring board (10) includes a substrate (11) that is transparent, a wiring pattern region (20) disposed on the substrate (11) and having first-direction wiring lines (21), and a feeding unit (40) electrically connected to the first-direction wiring lines (21) of the wiring pattern region (20). Each first-direction wiring line (21) has a first region (26) positioned near the feeding unit (40) and a second region (27) that is a region other than the first region (26). A line width (W.sub.3) of the first-direction wiring line (21) in the first region (26) is larger than a line width (W.sub.1) of the first-direction wiring line (21) in the second region (27).

The present disclosure provides a flexible circuit board for multiple signal transmission including a first dielectric layer; a plurality of first side grounds formed on one surface of the first dielectric layer to be parallel; first signal lines formed between the plurality of first side grounds; and a plurality of through holes which is formed in each of the plurality of first side grounds with an interval, along a length direction of the first side grounds.

According to one embodiment, a detection device includes a substrate, detection electrode, terminal formed of a metal material, lead, coating layer, conductive adhesion layer, and circuit board. The lead connects the electrode and the terminal. The coating layer covers the electrode and the lead, and partly covers the terminal. The adhesion layer covers a part of the terminal exposed from the coating layer and covers a part of the coating layer. The circuit board is connected to the terminal with the adhesion layer interposed therebetween. At least in an overlapping area where the adhesion layer covers the coating layer, an area of the metal material per unit area is smaller than that of the other area of the terminal.

A method is provided for mounting a semiconductor IC to a substrate without a socket or solder. The method includes disposing a guide structure on the substrate. The substrate has multiple contact pads disposed thereon. The substrate also has multiple nuts formed therein for connecting to one or more bolts. The method also includes placing the semiconductor IC inside the guide structure such that the semiconductor IC makes contact with the contact pads. A top plate is disposed on the semiconductor IC. Further, the top plate and the semiconductor IC are fastened to the substrate.