Patent classifications
H05K2201/09718
Loading Pads for Impedance Management in Printed Circuit Board
A printed circuit board (PCB) for three-dimensional (3D) packaging that may facilitate packaging multiple electronic components therein is provided. The PCB may include one or more loading pads formed around signal or ground vias to facilitate impedance control and reduce likelihood of signal distortion. The loading pads may be formed on a plane in a body of a dielectric layer configured to form the PCB.
Systems and methods for break out of interconnections for high-density integrated circuit packages on a multi-layer printed circuit board
A multi-layer printed circuit board having a first landing pad in a first layer and along a first axis arranged to receive a positive signal and a second landing pad in the first layer and along a second axis that is spaced away from the first axis longitudinally in the first layer and where the second landing pad arranged to receive a negative signal. A first buried in a second layer and along the first axis is spaced away from the first landing pad along the first axis. A second buried in the second layer and along the second axis is spaced away from the second landing pad along the second axis. A first signal connector provides a first electrical connection between the first landing pad and the second buried via and a second signal connector provides a second electrical connection between the second landing pad and the first buried via.
Arrangement for heat exchange
An arrangement for exchanging heat between two bodies comprises a circuit board, having at least one first via and at least one second via, wherein at least one heat exchange structure is integrated in the circuit board, wherein the at least one heat exchange structure comprises two heat exchange layers and an intermediate layer arranged between the two heat exchange layers, wherein the two heat exchange layers are thermally joined to each other and electrically separated from each other by the intermediate layer, wherein a first heat exchange layer is associated with the first body and can be brought into thermal contact with it and a second heat exchange layer is associated with the second body and can be brought into thermal contact with it, wherein the at least one first via and the at least one second via are each led through the two heat exchange layers and the intermediate layer arranged between the two heat exchange layers, wherein the at least one first via is in contact only with the first heat exchange layer and is insulated from the second heat exchange layer, and wherein the at least one second via is in contact only with the second heat exchange layer and is insulated from the first heat exchange layer.
CIRCUIT BOARD
A circuit board is disclosed, including a circuit board body and at least one via apparatus provided on the circuit board body. The via apparatus includes a via (101) formed on the circuit board body, a via pad (201) surrounding the via and separately provided from the via, and an electrical conductor (301) electrically connecting the via pad (201) with the via (101).
Medium voltage planar DC bus distributed capacitor array
An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.
Printed circuit board configuration to facilitate a surface mount double density QSFP connector footprint in a belly-to-belly alignment
An electronic device includes a printed circuit board (PCB). The PCB includes first and second grids disposed at a top surface and a bottom surface of the PCB, respectively. Each grid includes a plurality of footprint pins, and a plurality of vias extending through the PCB to the top and bottom surfaces. Each footprint pin includes a connecting end and a free end that opposes the connecting end. Each via includes a contact end located at one of grids and is in electrical contact with the connecting end of one of the footprint pins, and each via further includes a non-contact end that is located at the other of the grids and is not in electrical contact with any of the footprint pins. First and second connectors are mounted to the PCB top and bottom surfaces and connect with the footprint pins of the first and second grids.
POWER CONVERSION DEVICE
The power conversion device includes: a main circuit having first and second wiring layers formed respectively on both surfaces of a base board, mounted parts mounted on the first and second wiring layers, and first and second GND layers formed respectively, between external- and internal-layer portions of the base board and in regions corresponding to the mounted parts each being a mounted part which forms a circuit other than a circuit having an inductance component as a lumped constant, and to the first and second wiring layers; and a cooler attached to the base board by means of fixing screws through a first through-hole created in an end portion of the board; wherein the first and second GND layers are each formed so that creepage distance is created around a second through-hole in which a lead insertion part that mutually connects the first and second wiring layers is inserted.
Printed circuit board, printed wiring board, and electronic device
A printed circuit board includes an electrical component including a signal terminal, and a printed wiring board on which the electrical component is mounted. The printed wiring board includes a signal line connected to the signal terminal. The signal line includes a first line portion, a second line portion, a third line portion, and a fourth line portion disposed continuously in this order. The signal terminal is joined with the fourth line portion such that the signal terminal and the fourth line portion form an integral structure. A second characteristic impedance of the second line portion is lower than a first characteristic impedance of the first line portion. A third characteristic impedance of the third line portion is higher than the first characteristic impedance. A fourth characteristic impedance of the integral structure formed by the fourth line portion and the signal terminal is lower than the first characteristic impedance.
CIRCUIT BOARD COMPONENT AND TERMINAL
Provided are a circuit board component and a terminal. The circuit board component includes: a circuit board and a wire disposed on the circuit board, where the wire includes a first portion and a second portion, a line width of the first portion is greater than or equal to a line width threshold, and a line width of the second portion is less than the line width threshold.
MATING BACKPLANE FOR HIGH SPEED, HIGH DENSITY ELECTRICAL CONNECTOR
A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.