A modulated inductance module includes an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element formed on a semiconductor die, wherein the inductor further has two or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.50 mol % throughout said ceramic element, the ceramic element has crystalline grain structure having a diameter that is less than or equal to 1.5 a mean grain diameter, and the semiconductor die contains active semiconductor switches or rectifying components that are in electrical communication with the one or more electrical conductors of the inductor.

A capacitor-embedded substrate includes a first conductor layer that is a power-supply layer and divided into a first and second regions, a second conductor layer that is a ground layer, a dielectric layer between the first and second conductor layers, and a third conductor layer that is a power-supply layer and displaced from the dielectric layer along a thickness direction of the substrate, a first via by which the first region and the third conductor layer are coupled, the first via being not coupled to the second conductor layer, and a second via by which the second region and the third conductor layer are coupled, the second via being not coupled to the second conductor layer, wherein the third conductor layer includes a narrowed portion narrower than other portions in the third conductor layer, between a coupled portion to the first via and a coupled portion to the second via.

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

The present invention offers a device requiring a reduced number of manufacturing processes and providing high electrical reliability, and a method for manufacturing the device. The method for manufacturing the device forms through holes in a substrate, fills the through holes with a conductive material through electroplating from a first surface side of the substrate, polishes the conductive material to form through wirings, and forms an element portion on the first surface side. Then, the method processes the substrate so that the positions of the end faces of the through wirings measured from the substrate surface on the first surface side are made smaller in depth than the positions of the end faces of the through wirings measured from the substrate surface on the second surface side.

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

A material for forming of the capacitor layer which generates no crack in drilling on the dielectric layer of the capacitor in manufacturing of a highly multilayered printed wiring board embedded a capacitor circuit. Copper clad laminate for forming of an embedded capacitor layer of a multilayered printed wiring board including an embedded capacitor circuit having a layer structure of copper layer/dielectric layer of the capacitor/copper layer in an inner layer characterized in that the composite elastic modulus Er of the resin film constituting the dielectric layer of the capacitor along the thickness direction is less than 6.1 GPa is employed.

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

A power management module, provides an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element including one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.50 mol % throughout the ceramic element.

The disclosure relates to a printed circuit board having at least two current-conducting layer plies, wherein the current-conducting layer plies extend in an axial direction of the printed circuit board and are arranged in succession in a thickness direction of the printed circuit board. A component fastened by THT is arranged on one side of the printed circuit board. At least one connecting element extends through the printed circuit board through a passage opening in the thickness direction. The current-conducting layer ply is adjacent to the component fastened by THT reaches as far as the connecting element and the current-conducting layer ply that is remote from the component fastened by THT is at a distance from the connecting element.

Embodiments of the invention include a microelectronic device that includes a substrate having transistor layers and interconnect layers including conductive layers to form connections to transistor layers. A capacitive bump is disposed on the interconnect layers. The capacitive bump includes a first electrode, a dielectric layer, and a second electrode. In another example, an inductive bump is disposed on the interconnect layers. The inductive bump includes a conductor and a magnetic layer that surrounds the conductor.