A system package module is provided. The system package module includes a module substrate, a plurality of first pins and a plurality of second pins. The module substrate includes a module substrate surface. The module substrate surface includes a first pin arrangement area and a second pin arrangement area. The second pin arrangement area surrounds the first pin arrangement area. The first pins are disposed in the first pin arrangement area. A first pin gap is formed between the two adjacent first pins. The second pins are disposed in the second pin arrangement area. A second pin gap is formed between the two adjacent second pins. The first pin gap is greater than the second pin gap.

Aspects of the disclosure provide a package system that includes a first integrated circuit (IC) package and a second IC package. The first IC package includes a first IC chip mounted on a first substrate-chip surface of a first package substrate. The first package substrate includes first near-conductive layers that are closer to the first substrate-chip surface than first far-conductive layers. The second IC package includes a second IC chip mounted on a second substrate-chip surface of a second package substrate. The second package substrate includes second near-conductive layers that are closer to the second substrate-chip surface than second far-conductive layers. A first contact structure on the first substrate-chip surface and a second contact structure on the second substrate-chip surface electrically couple the first IC chip with the second IC chip through electrical connections in the first and second near-conductive layers.

Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Systems and methods for the design and use of a System-in-Package (SiP) device with a connection layout for minimizing a system Printed Circuit Board (PCB) using the SiP are provided.

Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.

A connector with a tolerance module includes a socket and a plug adapted to the socket, wherein the socket includes a first housing, the plug includes a tolerance module and a third housing, the tolerance module includes a second housing, the second housing includes second contact members, the second housing is movably arranged on the third housing in a direction perpendicular to the axial direction of the connector, and the second contact members are floatingly assembled in the second housing to enable displacement in the direction perpendicular to the axial direction of the connector. The second housing only generates translational motion without displacement when the connector is inserted. The tolerance of the plug and the socket is realized by the floating assembly of the second contact members in the second housing.

Systems and methods for providing a PWB. The methods comprise: forming a Core Substrate (CS) a First Via (FV) formed therethrough; disposing a First Trace (FT) on an exposed surface of CS that is in electrical contact with FV; laminating a first HDI substrate to CS such that FT electrically connects FV via with a Second Via (SV) formed through the first HDI substrate; disposing a Second Trace (ST) on an exposed surface of the first HDI substrate that is in electrical contact with SV; and laminating a second HDI substrate to the first HDI substrate such that ST electrically connects SV to a Third Via (TV) formed through the second HDI substrate. SV comprises a buried via with a central axis spatially offset from central axis of FV and SV. FV and SV have diameters which are smaller than TV's diameter.

A system package module is provided. The system package module includes a module substrate, a plurality of first pins and a plurality of second pins. The module substrate includes a module substrate surface. The module substrate surface includes a first pin arrangement area and a second pin arrangement area. The second pin arrangement area surrounds the first pin arrangement area. The first pins are disposed in the first pin arrangement area. A first pin gap is formed between the two adjacent first pins. The second pins are disposed in the second pin arrangement area. A second pin gap is formed between the two adjacent second pins. The first pin gap is greater than the second pin gap.

A cable socket connector assembly for an electronic system includes a socket assembly having a socket substrate including socket substrate conductors. The socket assembly has socket contacts extending between terminating ends and mating ends with the terminating ends terminated to corresponding socket substrate conductors and the mating ends configured to be terminated to corresponding package contacts of an electronic package of the electronic system. The cable socket connector assembly includes a cable assembly terminated to the socket assembly having an array of cables each having a cable conductor terminated to a corresponding socket substrate conductor. The socket contacts and the corresponding socket substrate conductors define electrical paths between the cable conductors of the cables and the package conductors of the electronic package.

A package device is provided. The package device includes a substrate, a plurality of upper lands disposed on one surface of the substrate, a plurality of upper solder balls disposed on the plurality of upper lands, a die connected to the plurality of upper solder balls, a plurality of lower lands disposed on the other surface of the substrate, a plurality of lower solder balls disposed on some of the plurality of lower lands, and a capacitor connected to the lower lands on which the plurality of lower solder balls are not disposed among the plurality of lower lands, provided on an opposite side of the die, and including a height greater than the height of the plurality of lower solder balls.