A socket connector includes a socket assembly having a socket frame, a socket substrate coupled to the socket frame and socket contacts terminated to the socket substrate. The socket substrate has first and second upper mating areas including first and second socket substrate conductors for mating with an electronic package and an electrical component, respectively. The socket contacts define an interface with the electronic package. The socket assembly is configured to electrically connect the electronic package with both a host circuit board and the electrical component.

A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.

An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

A manufacturing method for a circuit board in which a pin inserted in a through-hole of a land is welded to the land is disclosed. The land is covered with a white layer, and an irradiation angle of a laser beam with respect to the circuit board is adjusted so that reflected light of the laser beam emitted to the pin reaches the white layer on the land. As the reflected light of the laser beam is allowed to reach a white region provided on the land, the reflected light is scattered on the white region. A rate of absorption of the laser beam by the land is decreased, and a temperature increase of the land is restrained. As a result, a damage of an insulating part around the land is restrained.

A method of manufacturing a component carrier is disclosed. The method includes galvanically depositing at least part of at least one electrically conductive pillar on a component, and inserting the at least one electrically conductive pillar and an electrically insulating layer structure into one another.

Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

A socket connector includes a socket assembly having a socket substrate and socket contacts. The socket substrate has first and second upper mating areas and a first lower mating area. The socket substrate has first and second socket substrate conductors at the first and second upper mating areas, respectively, and third socket substrate conductors at the first lower mating area electrically connected to corresponding first socket substrate conductors. The first socket substrate conductors are electrically connected to an electronic package, the second socket substrate conductors are electrically connected to an electrical component and the third socket substrate conductors are electrically connected to a host circuit board. The socket assembly is configured to electrically connect the electronic package with both the host circuit board and the electrical component. The socket contacts have a terminating end terminated to corresponding first socket substrate conductors and a mating end mated to package contacts.

An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.