A multilayer ceramic capacitor includes a multilayer body including dielectric layers, first inner electrodes, and second inner electrodes stacked on one another, a first outer electrode electrically connected to the first inner electrodes, and a second outer electrode electrically connected to the second inner electrodes. The multilayer body includes first and second side surfaces respectively including first and second recesses where a midsection of each of the first and second side surfaces in a length direction is recessed inward in a width direction. When the multilayer ceramic capacitor is viewed in a stacking direction, a dimension of each of the first and second recesses in the length direction is smaller on an inner side than on an outer side in the width direction.

A substrate assembly includes a printed circuit (PC) substrate, first and second microchips, components or substrates mounted on a surface of the PC substrate, and a projection extending in spaced relation to the surface of the PC substrate. In one example, the projection extends between (i) a downward facing surface and/or an edge of a side facing surface proximate the downward facing surface of the first microchip, component or substrate and (ii) an upward facing surface and/or an edge of a side facing surface proximate the upward facing surface of the first microchip, component or substrate. The first and second microchips, components or substrates may be mounted on different levels of the PC substrate surface. In another example, the projection extends between a upward and/or side facing surface of a first microchip, component or substrate and a slot or cavity in a second microchip, component or substrate.

Through-hole mounted semiconductor assemblies are described. A printed circuit board (“PCB”) has first and second PCB sides and has a through hole therein. The through hole defines a hole area. A semiconductor package may be disposed in the hole area such that the semiconductor package is at least partially exposed on one or more of the first and the second PCB sides. Package contacts on the semiconductor package may be electrically coupled to PCB contacts disposed on one or more of the PCB sides. In some embodiments, one or more support structures may be coupled to the PCB and may touch the semiconductor package. In some embodiments, cooling devices may be placed in thermal communication with the semiconductor package on both sides of the PCB.

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate. Bottommost conductive layer is disposed on bottommost dielectric layer and electrically connects to metallization layer. First build-up stack includes more conductive and dielectric layers than second build-up stack.

An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.

An example method for attaching a ball grid array chip to a circuit board includes providing an adapter for attaching a chip with a plurality of solder balls to a circuit board, the adapter having an adapter substrate made from a material having substantially the same coefficient of thermal expansion as the substrate used in the chip and having at least one electrical contact site on a mounting surface of the adapter substrate for engaging a solder ball on the ball grid array chip and a plurality of lead wires extending from each side of the adapter substrate. At least one of the lead wires is electrically connected to at least one electrical contact site on the adapter substrate.

Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops. The capacitive interconnects can be utilized in a semiconductor package, providing a compact assembly that can reduce the utilization of real estate in a board substrate onto which the semiconductor package is mounted.

A printed circuit board includes: an insulating member; a first bump disposed on the insulating member; a second bump disposed adjacently to but spaced apart from the first bump on the insulating member; a first insulating wall covering at least a portion of the first bump; and a second insulating wall covering at least a portion of the second bump and disposed adjacently to but spaced apart from the first insulating wall.