A semiconductor device including a substrate; bottom electrodes on the substrate, each bottom electrode including a first region and a second region, the second region containing an additional element relative to the first region; a first supporting pattern on the substrate and in contact with a portion of a side surface of each bottom electrode; a top electrode on the bottom electrodes; a dielectric layer between the bottom electrodes and the top electrode; and a capping layer between the bottom electrodes and the dielectric layer, the capping layer covering a top surface and a bottom surface of the first supporting pattern, wherein the second region is in contact with the capping layer, and the capping layer and the dielectric layer include different materials from each other.

A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

A semiconductor device of the disclosure includes a substrate, a capacitor contact structure electrically connected to the substrate, a lower electrode connected to the capacitor contact structure, a capacitor insulating layer covering the lower electrode, and an upper electrode covering the capacitor insulating layer. The upper electrode includes a multiple layer on the capacitor insulating layer, and a cover layer on the multiple layer. The multiple layer includes a first electrode layer, a second electrode layer, and a first metal silicide layer between the first and second electrode layers. A work function of the first metal silicide layer is greater than a work function of the first electrode layer and a work function of the second electrode layer.

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a front end of line (FEOL) structure, and a metallization structure. The FEOL structure is disposed over the substrate. The metallization structure is over the FEOL structure. The metallization structure includes a transistor structure, an isolation structure, and a capacitor. The transistor structure has a source region and a drain region connected by a channel structure. The isolation structure is over the transistor structure and exposing a portion of the source region, and a side of the isolation structure has at least a lateral recess vertically overlaps the channel structure. The capacitor is in contact with the source region and disposed conformal to the lateral recess. A method for manufacturing a semiconductor structure is also provided.

Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

The present application relates to a mask structure, a semiconductor structure and methods for manufacturing the same. The method for manufacturing a mask structure includes: dividing an overall structure into two regions, and developing the array region and the periphery region with a negative photoresist.

A method for forming a semiconductor device includes the following operations. A stacked structure is provided, which includes a substrate, and sacrificial layers and semiconductor layers alternately stacked on surface of the substrate. Multiple first grooves and semiconductor pillars extending in first direction are included in the sacrificial layers and the semiconductor layers. Word line pillars are formed in second direction, intersect with the semiconductor pillars and surround the semiconductor pillars. Sources and drains are formed respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process. Bit lines are formed on a side of the sources or the drains, are connected with same, and extend in third direction. The first, second and third directions are pairwise perpendicular. Capacitors are formed on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.

Embodiments provide a semiconductor structure and a method thereof. The method includes: providing a first substrate, and forming a drive pad on the first substrate; providing a second substrate, and forming active pillars and a bit line in sequence on a side of the second substrate, wherein a side of the bit line is connected to the active pillars, and a surface of the bit line facing away from the active pillars is exposed on a surface of the second substrate; bonding the bit line to the drive pad correspondingly; thinning the second substrate from a side of the second substrate facing away from the first substrate until the active pillars are exposed; and forming a storage capacitor on sides of the active pillars facing away from the drive pad, the storage capacitor being connected to the active pillars.