Embodiments of the present invention provide a structure and method for fabrication of deep trenches in semiconductor-on-insulator structures. An upper portion of the deep trench cavity is formed to expose a sidewall of the buried insulator layer. A protective layer is disposed on the sidewall of the buried insulator layer. Then, the cavity is extended into the bulk substrate. The protective layer prevents over etch of the buried insulator layer during this process. The protective layer is then partially removed, such that the semiconductor-on-insulator (SOI) layer sidewall is exposed. The trench is then filled with a conductive fill material, such as polysilicon. The protection of the buried insulator (BOX) layer allows the trenches to be placed closer together while reducing the risk of a short circuit due to over etch, thereby increasing circuit density and product yield.

A semiconductor device for a volatile memory is disclosed. The semiconductor device includes a substrate, a side wall and an epitaxial liner. The substrate has a first height and is made of a first material having a first lattice parameter. The side wall defines a deep trench. The epitaxial liner is disposed around the side wall, is made of a second material having a second lattice parameter, and has a second height having a same level with the first height, wherein the epitaxial liner and the side wall cooperate for creating a desired aspect ratio for the deep trench.

The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

A semiconductor structure and a manufacturing method thereof are disclosed in embodiments of the present disclosure. The semiconductor structure includes: a substrate; a plurality of discrete bottom electrodes located on the substrate; and a first dielectric layer and a second dielectric layer; where the first dielectric layer and the second dielectric layer are located between the bottom electrodes; the second dielectric layer is located between the first dielectric layer and each of the bottom electrodes; and a thickness of an upper portion of the second dielectric layer is less than a thickness of the bottom of the second dielectric layer.

A semiconductor structure includes a substrate, a drain region, a word line, a gate structure, and a first bit line. The drain region is disposed on the substrate. The gate structure is disposed on the drain region and has a portion in the word line. The first bit line is disposed on the gate structure to serve as a source region.

A memory structure includes a substrate, an isolation area, a plurality of active areas and a first word line. The isolation area and the active areas are formed on the substrate. The isolation area surrounds the active areas, and the isolation area comprises an isolation structure formed in an isolation trench recessed in the isolation area. The first word line is formed across a first active area of the active areas and the isolation area. The first word line has a first width in the first active area and a second width in the isolation area. The first width is less than the second width.

Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer. A fifth-dielectric layer forms on the fourth-dielectric layer and the fifth-conductive layer.

The present disclosure provides a semiconductor device, a semiconductor structure and a formation method thereof, and relates to the field of semiconductor technologies. The formation method includes: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer to form trenches and through holes distributed side by side in the sacrificial layer; forming insulating layers covering a sidewall of the trench and a sidewall of the through hole; sequentially forming a conductive layer and a passivation layer in the trench and the through hole to form a bitline structure in the trench; and removing the passivation layer in the through hole to form a capacitor contact structure in the through hole.