A semiconductor device may include a word line stack over a substrate; a plurality of supporters including vertically extending blocking spacers to support the word line stack; and storage nodes of a capacitor disposed laterally between the supporters.

Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.

A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

A manufacturing method of a semiconductor device includes forming an opening in a substrate, implanting a dopant in the substrate from a sidewall of the opening such that a doping region is formed in the substrate at the sidewall of the opening, filling a dielectric material in the opening to form a first dielectric structure after implanting the dopant in the substrate from the sidewall of the opening, and forming a passing word line in the dielectric structure.

A semiconductor device includes a vertical stack of ring-shaped electrodes that are electrically connected together into a top electrode of a capacitor, on a semiconductor substrate. A bottom electrode of the capacitor is also provided, which extends vertically in a direction orthogonal to a surface of the substrate and through centers of the vertical stack of ring-shaped electrodes. An electrically insulating bottom supporting pattern is provided, which extends between a lowermost one of the ring-shaped electrodes and an intermediate one of the ring-shaped electrodes.

Embodiments of the present disclosure relate to a semiconductor structure and a manufacturing method thereof, a data storage device and a data read-write device. The semiconductor structure includes: a substrate, a plurality of active regions separated from each other being formed in the substrate; a trench, located in the active region; a first gate structure, located in the trench, and configured to be applied with a first applied voltage; a second gate structure, located in the trench, and located above the first gate structure, and configured to be applied with a second applied voltage, the second applied voltage being greater than the first applied voltage; and an insulating isolation layer, located in the trench, and located between the first gate structure and the second gate structure.

A semiconductor device includes bottom electrodes on a substrate. A supporting pattern is disposed between the bottom electrodes in a plan view. A top electrode covers the bottom electrodes and the supporting pattern. A dielectric layer is disposed between the bottom electrodes and the top electrode and between the supporting pattern and the top electrode. A capping pattern is interposed between the bottom electrodes and the dielectric layer and between the supporting pattern and the dielectric layer. The capping pattern covers at least a portion of a side surface of the supporting pattern and extends to cover a top surface of the supporting pattern and top surfaces of the bottom electrodes.

A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate having a first surface and a second surface opposite to each other; and forming, in the substrate, active areas arranged in an array and an isolation structure configured to isolate the active areas. Each of the active areas includes a source region, a drain region, and a channel region positioned between the source region and the drain region, where the source region is exposed to the first surface. The source region includes a first region and a second region distributed in a horizontal direction, where the first region and the second region have different doping types, and the drain region and the source region are not positioned on the same surface.