The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.

The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

A memory device includes a substrate, a transistor, and a memory cell. The substrate includes a cell region and a logic region. The transistor is over the logic region and includes a first metal gate stack. The memory cell is over the cell region and includes an erase gate. The erase gate is a metal gate stack.

A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.