An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.

A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

An organic thin film transistor includes a gate electrode, an organic semiconductor layer overlapped with the gate electrode, a hydrophilic nanolayer on the organic semiconductor layer, and a source electrode and a drain electrode electrically connected to the organic semiconductor layer.

A method for depositing nanostructures on a substrate comprises: forming a patterned alignment layer on a surface of the substrate, wherein the patterned alignment layer has one or more cavities each having a main region for accommodating at least one template nanostructure therein and a plurality of extension regions extending from the main region and in fluid communication with the main region, and wherein the plurality of extension regions are sized and shaped to not accommodate the at least one template nanostructure; and diffusing template nanostructures into the one or more cavities of the patterned alignment layer.

A thin film transistor array panel and a manufacturing method are disclosed herein. The thin film transistor array panel includes a data line, a first block of a source electrode, a third block of a drain electrode, and an electrode layer which are formed by a first metal layer disposed on a baseplate; a second block of the source electrode, a fourth block of the drain electrode are formed by a second metal layer which is disposed on the first metal layer. The first block and the second block overlap to combine integrally. The third block and the fourth block overlap to combine integrally. The present invention can decrease the electrical resistance of each of the source electrode and the drain electrode.

A transistor has a substrate, source and drain electrodes on the substrate, the source and drain electrodes formed of a conductor ink having silver nanoparticles with integrated dipolar surfactants, an organic semiconductor forming a channel between the source and drain electrodes, the organic semiconductor in contact with the source and drain electrodes, a gate dielectric layer having a first surface in contact with the organic semiconductor, and a gate electrode in contact with a second surface of the gate dielectric layer, the gate electrode formed of silver nanoparticles with integrated dipolar surfactants.

The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer block B is attached to the polymer block A, and wherein at least 60 mol % of the repeat units of polymer block B are selected from the group consisting of Formulas (1A), (1B), (1C), (1D), (1E) and (1F), wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5, R.sup.6, R.sup.7 and R.sup.8 are independently and at each occurrence H or C.sub.1-C.sub.10-alkyl. ##STR00001##

A method of p-type doping a carbon nanotube includes the following steps: providing a single carbon nanotube; providing a layered structure, wherein the layered structure is a tungsten diselenide film or a black phosphorus film; and p-type doping at least one portion of the carbon nanotube by covering the carbon nanotube with the layered structure.

The present invention provides compounds of formula ##STR00001##
a process for their preparation, a solution comprising these compounds, a process for the preparation of a device using the solution, devices obtainable by the process and the use of the bis-azide-type compounds as cross-linkers.

A method of making N-type semiconductor layer includes following steps. An insulating substrate is provided. An MgO layer is deposited on the insulating substrate. A first dielectric layer is formed by acidizing the MgO layer. A semiconductor carbon nanotube layer is formed to cover the MgO layer. A source electrode and drain electrode are formed to be electrically connected to the semiconductor carbon nanotube layer. A second dielectric layer is applied on the semiconductor carbon nanotube layer. A gate electrode is formed on the second dielectric layer.