A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.

Integrated circuit structures, arrangements, and manufacturing processes are discussed herein. In one example, a method of forming a transistor structure includes forming a dielectric layer onto a gate element and forming a corrugated surface into the dielectric layer using at least an atomic layer etching (ALE) process to remove portions of the dielectric layer. The method also includes forming a semiconductor layer onto the corrugated surface and forming a source element and a drain element onto the semiconductor layer.

A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric material and the electrode. Related semiconductor devices comprising at least one transistors, related electronic systems, and related methods are also disclosed.

Disclosed by the present disclosure are an organic thin film transistor structure and a manufacturing method, a gas sensor, and a related apparatus: a gap, which contacts an organic active layer and which is used for accommodating a gas to be detected, is provided in the organic thin film transistor structure.

A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

A driving substrate includes a substrate, a plurality of active devices, a thermal-conducting pattern layer and a buffer layer. The active devices are separately arranged on the substrate. Each active device includes a gate, a channel layer, a gate insulation layer, a source and a drain. The source and the drain expose a portion of the channel layer to define a channel region. The thermal-conducting pattern layer is disposed on the substrate and includes at least one thermal-conducting body and at least one thermal-conducting pattern connected to the thermal-conducting body. The thermal-conducting pattern corresponds to a location of at least one of the channel region, the channel layer, the gate, the source and the drain and each active device. The buffer layer is disposed on the substrate and covers the thermal-conducting pattern layer, and is located between the thermal-conducting pattern and each active device.

The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.

A thin film transistor includes an active layer on a substrate, a gate electrode configured to be spaced from the active layer and partially overlapped with the active layer, and a gate insulating layer, at least a part of the gate insulating layer being disposed between the active layer and the gate electrode, wherein the gate insulating layer includes a first gate insulating layer between the active layer and the gate electrode, and a second gate insulating layer configured to have a dielectric constant (k) which is different from a dielectric constant of the first gate insulating layer, and disposed in a same layer as the first gate insulating layer, and wherein at least a part of the second gate insulating layer is disposed between the active layer and the gate electrode.

An organic thin film transistor includes a drain electrode, a semiconductor layer, a source electrode, a gate insulator, and a gate electrode. A horizontal portion and a vertical portion of the semiconductor layer are respectively located on a top surface and an end surface of the drain electrode, and the drain electrode protrudes from the horizontal portion in a first direction. The source electrode is disposed along a surface of the semiconductor layer. The source electrode has an extending portion that extends in a second direction opposite to the first direction. The gate insulator is disposed along a top surface and two side surfaces of a stacked structure defined by the drain electrode, the semiconductor layer, and the source electrode. The gate electrode is located on the gate insulator, and a portion of the gate insulator is between the stacked structure and the gate electrode.

Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.