One aspect of this invention relates to an ohmic-contact-gated transistor (OCGT), comprising a bottom gate electrode formed on a substrate; a first dielectric layer formed on the bottom gate electrode; a thin film formed of a semiconducting material on the first dielectric layer; a bottom contact formed on a part of the thin film; a second dielectric layer conformally grown on the bottom contact to result in a self-aligned dielectric extension from the bottom contact on the thin film; and a top contact formed on the second dielectric layer on the top of the bottom contact and fully overlapping with the dielectric extension to define a device channel in the thin film under the dielectric extension between the bottom contact and the top contact.

A thin film transistor includes a gate electrode, a semiconductor layer overlapped with the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer. The semiconductor layer includes a plurality of holes. The gate insulating layer may include a plurality of recess portions at a surface of the gate insulating layer facing the semiconductor layer. A method of manufacturing the thin film transistor is provided. A thin film transistor array panel and an electronic device may include the thin film transistor.

Disclosed is a nanofilm, a thin film transistor and manufacture methods thereof. The nanofilm of the present disclosure comprises a plurality of regions distributed in a film plane dimension, wherein each of the regions is composed of one kind of nanomaterial, and nanomaterials of adjacent regions are different from each other and contact with each other to form a heterojunction or a Schottky junction.

A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.

Disclosed by the present disclosure are an organic thin film transistor structure and a manufacturing method, a gas sensor, and a related apparatus: a gap, which contacts an organic active layer and which is used for accommodating a gas to be detected, is provided in the organic thin film transistor structure.

An object is to provide a bottom gate type organic semiconductor transistor in which a sufficient carrier mobility is exhibited, a variation in performance between elements is small, and power consumption is also suppressed.

Provided is a bottom gate type organic semiconductor transistor including: a gate insulating layer; and an organic semiconductor layer that is disposed adjacent to the gate insulating layer. in which a surface free energy of a surface of the gate insulating layer on the organic semiconductor layer side is 20 to 50 mN/m, an arithmetic average roughness Ra of the surface of the gate insulating layer on the organic semiconductor layer side is 2 nm or lower, and the organic semiconductor layer includes a compound represented by the following Formula (1) that has a molecular weight of 3000 or lower.

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X, Y, and Z each independently represent a specific ring-constituting atom. R.sup.1 and R.sup.2 each independently represent a hydrogen atom, an alkyl group, an alkenyl group, an alkynyl group, an aryl group, or a heteroaryl group, and R.sup.3 and R.sup.4 each independently represent a halogen atom, an alkyl group, an alkenyl group, an alkynyl group, an aryl group, or a heteroaryl group. m and n each independently represent an integer of 0 to 2.

According to example embodiments, a method includes dispersing carbon nanotubes in a mixed solution containing a solvent, the carbon nanotubes, and a dispersant, the carbon nanotubes including semiconducting carbon nanotubes, the dispersant comprising a polythiophene derivative including a thiophene ring and a hydrocarbon sidechain linked to the thiophene ring. The hydrocarbon sidechain includes an alkyl group containing a carbon number of 7 or greater. The hydrocarbon sidechain may be regioregularly arranged, and the semiconducting carbon nanotubes are selectively separated from the mixed solution. An electronic device includes semiconducting carbon nanotubes and the foregoing described polythiophene derivative.

The disclosure relates to a logic circuit. The logic circuit includes two ambipolar thin film transistors. Each of the two ambipolar thin film transistors includes a substrate; a semiconductor layer located on the substrate and including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are located on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The two ambipolar thin film transistors share the same substrate, the same gate, and the same drain.

The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.

A thin film transistor and its manufacturing method, an array substrate and a display device are disclosed, the thin film transistor is of a gate bottom contact type, and includes a gate electrode (3) and a gate insulation layer (2), the gate insulation layer (2) is provided with a recess (4) at a position corresponding to the gate electrode (3). With the thin film transistor, the problem of wire breakage in the active layer at the channel between the source/drain electrodes can be avoided, the performance and stability of the thin film transistor is improved, and the production cost is lowered down.