A method for making thin film transistor includes: providing a gate electrode and forming an insulating layer on the gate electrode; providing a carbon nanotube film comprising a plurality of metallic carbon nanotubes and a plurality of semiconducting carbon nanotubes; laying the carbon nanotube film on a surface of the insulating layer, and placing the carbon nanotube film under a scanning electron microscope to take photo of the carbon nanotube film to distinguish the plurality of metallic carbon nanotubes and the plurality of semiconducting carbon nanotubes; removing the metallic carbon nanotubes, and forming a source electrode and a drain electrode on a surface of the semiconducting layer.

A method for making thin film transistor includes: providing a gate electrode and forming an insulating layer on the gate electrode; providing a carbon nanotube film comprising a plurality of metallic carbon nanotubes and a plurality of semiconducting carbon nanotubes; laying the carbon nanotube film on a surface of the insulating layer, and placing the carbon nanotube film under a scanning electron microscope to take photo of the carbon nanotube film to distinguish the plurality of metallic carbon nanotubes and the plurality of semiconducting carbon nanotubes; removing the metallic carbon nanotubes, and forming a source electrode and a drain electrode on a surface of the semiconducting layer.

An electronic or optoelectronic device includes: (1) a semiconductor layer; (2) a pair of electrodes electrically coupled to the semiconductor layer; and (3) a dielectric layer in contact with the semiconductor layer and including a polar elastomer, where the elastomer has a glass transition temperature T.sub.g that is no greater than 25 C.

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

An electronic component (1) and an electronic device (100) comprising one or more such components (1). The electronic component (1) comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one insulating or semi-insulating layer (7) between said electrodes. The stack further comprises a buffer layer (13), arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

A synaptic transistor based on a metal nano-sheet and a method thereof are provided. A self-assembled floating gate layer is formed. The floating gate layer prevents leakage of electric charges transmitted from a channel layer, and also temporarily stores the transmitted electric charge. Thus, the synaptic transistor may be used as an effective memory for storing.

The present invention relates to a process for functionalizing a surface of semi-conductors, conductors, and dielectrics using an amine-borane bearing a functionality from a group of, but not limited to, alkene, alkyne, hydroxyl, thiol, acetal, ester, amide, nitrile, nitro, or alkoxysilane, under a mild condition. Products of this facile process are also in the scope of this disclosure.

Disclosed are new compounds having semiconducting properties. Such compounds can be processed in solution-phase at a temperature of less than about 50 C. into thin film semiconductors that exhibit high carrier mobility and/or good current modulation characteristics.

A method for producing a thin film transistor and a thin film transistor that can suppress deterioration and variation in performance are provided. A method for producing a thin film transistor includes: forming an organic semiconductor layer on a first main surface of a substrate; forming a first conductive layer on the organic semiconductor layer, while forming a second conductive layer on a second main surface of the substrate; forming mask layers collectively on the first conductive layer and the second conductive layer; and bringing the first conductive layer and the second conductive layer collectively into contact with etching liquid so that partial regions of the first conductive layer and the second conductive layer are removed, so as to form a source electrode and a drain electrode on the organic semiconductor layer, while to form a gate electrode on the second main surface of the substrate.

A vertical channel field-effect transistor is taught. The vertical channel field-effect transistor comprises a primary substrate and a secondary substrate. A bottom conducting layer is provided on the primary substrate. A top conducting layer is transferred from a secondary substrate to the primary substrate by using an insulating adhesive layer. The thickness of the insulating adhesive layer defines the channel length. The portion of the top conducting layer which is over the bottom conducting layer defines the maximum possible channel. At least one semiconducting layer is provided on and around a perimeter of at least a portion of the channel width. At least one insulating layer is provided on at least a portion of the at least one semiconducting layer. At least one gate conducting layer provided on at least a portion of the at least one insulating layer.