Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer so as to cover the first insulator layer; forming a base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the base film, forming a gate electrode on the surface of the base film by electroless plating, wherein the forming of the base film is performed by applying a liquid substance which is a formation material of the base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer.

Laminate, method of manufacturing laminate, transistor, and method of manufacturing transistor using a composition having the following (a) to (c): (a) a first organic compound represented by Formula (1) below (R represents a hydrogen atom or a glycidyl group. A plurality of Rs may be identical to or different from each other, but each of at least two Rs is a glycidyl group), (b) a second organic compound represented by Formula (2) below, and (c) a photocationic polymerization initiator

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A flexible array substrate structure and manufacturing method thereof are disclosed, in which the patterning process of an organic semi-conductive layer is achieved by using the inside wall of the opening of a color film layer as a bank, so that one mask can be saved. Also, a process for manufacturing a device can be simplified by an improved device structure, so that the flexible array substrate structure of the invention can be obtained by only using four masks.

The metal thin film production method of the present invention includes, in the following order, the steps of: preparing a substrate (1) having thereon an underlayer (2) formed of an insulating resin; subjecting a surface of the underlayer (2) to a physical surface treatment for breaking bonds of organic molecules constituting the insulating resin; subjecting the substrate (1) to a heat treatment at a temperature of 200° C. or lower; applying a metal nanoparticle ink to the underlayer (2); and sintering metal nanoparticles contained in the metal nanoparticle ink at a temperature equal to or higher than a glass transition temperature of the underlayer (2). A fused layer (4) having a thickness of 100 nm or less is formed between the underlayer (2) and a metal thin film (3) formed by sintering the metal nanoparticles.

A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

The present invention relates to organic thin film transistors and the preparation and use thereof in sensing applications, and in particular in glucose sensing applications.

Electronic ratchet devices comprising a pair of first and second electrodes; a dielectric layer; a gate electrode layer; and a transport layer are disclosed herein.

What is provided is a pattern forming method for forming a pattern on a surface to be processed of an object, the method including: a first layer forming step of forming a first layer containing a compound having a protective group that is decomposable by an acid and also decomposable by light, on the surface to be processed; a second layer forming step of forming a second layer containing a photoacid generator that is configured to generate an acid by exposure, on the first layer; an exposure step of exposing the first layer and the second layer to form a latent image including an exposed region and an unexposed region, on the first layer; and a disposition step of disposing a pattern forming material in the exposed region or the unexposed region.