A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

Gated organic light-emitting diodes or vertical light emitting transistors are disclosed based on the modulation of charge carrier injection from electrodes into light-emitting materials by applying external gate potential. This gate modulation were achieved in two disclosed methods: 1) a porous electrode allowing mobile ions to stabilize electrochemically doped semiconducting materials that can form ohmic contact with electrodes: 2) an electrode with gate-tunable work function such as Al:LiF composite electrodes.

A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (L.sub.G) or contact length (L.sub.C). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6 improvement to EDP compared to top-gate CNFETs.

Provided are a display substrate and a preparation method thereof, a display panel, and a display device. The display substrate includes a substrate and a plurality of pixel units on the substrate. The pixel unit comprises a plurality of functional layers that are sequentially arranged in a direction away from the substrate. At least one of the plurality of functional layers, which is close to the substrate, constitutes a vertical thin film transistor (VTFT). At least one of the plurality of functional layers, which is away from the substrate, constitutes an organic light-emitting transistor (OLET). An orthographic projection region of the OLET on the substrate and an orthographic projection region of the VTFT on the substrate at least partially overlap.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

A semiconductor device includes a substrate, a nanotube structure, and a gate structure. The nanotube structure is disposed over the substrate. The nanotube structure includes a semiconducting carbon nanotube (s-CNT) and a first insulating nanotube. The first insulating nanotube has an inert surface on the s-CNT. The gate structure includes a first metallic carbon nanotube (m-CNT) over the nanotube structure.

An organic thin film transistor (OTFT) is provided. The OTFT includes a substrate, a first electrode layer disposed on a top surface of the substrate, an organic active layer disposed on a top surface of the first electrode layer, a second electrode layer disposed in the organic active layer and including a base electrode, a plurality of pinholes formed in the base electrode and providing charge transfer paths, and a metal oxide configured to surround a surface of the base electrode and the pinholes, and a third electrode layer disposed on the organic active layer.

A semiconductor device includes a substrate, a nanotube structure, and a gate structure. The nanotube structure is disposed over the substrate. The nanotube structure includes a semiconducting carbon nanotube (s-CNT) and a first insulating nanotube. The first insulating nanotube has an inert surface on the s-CNT. The gate structure includes a first metallic carbon nanotube (m-CNT) over the nanotube structure.

In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

Devices, structures, materials and methods for carbon enabled vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Carbon electrodes (such as from graphene) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, carbon electrodes and relevant substrates and gates are utilized to construct LETs, including heterojunction VOLETs.