In some examples, a half-bridge circuit includes a first switch including a first load terminal, a second load terminal, a first control terminal, and a second control terminal that is electrically isolated from the first control terminal of the first switch. The half-bridge circuit further includes a second switch including a first load terminal electrically connected to the second load terminal of the first switch, a second load terminal, and a control terminal.

Devices, structures, materials and methods for vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Porous conductive transparent electrodes (such as from nanowires (NW)) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, porous conductive electrodes and relevant substrates and gates are utilized to construct LETs, including singly and doubly gated VPLETs. In addition, printing processes are utilized to deposit layers of one or more of porous conductive electrodes, LEDs, and dielectric materials on various substrates to construct LETs, including singly and doubly gated VPLETs.

Structures for a bitcell of a two-port static random access memory (SRAM) and methods for forming a structure for a bitcell of a two-port SRAM. A storage element of the SRAM includes a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) VTFET with a fin that is aligned in a first row with the fin of the first PU VTFET, a second PU VTFET with a fin, and a second PD VTFET with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port pull-down (RPD) VTFET with a fin and a read port access (RPG) VTFET with a fin that is aligned in a third row with the fin of the RPG VTFET.

A method for forming an organic thin film transistor is provided. An organic semiconductor layer, a source electrode, a drain electrode, a gate electrode, and an insulating layer are formed on an insulating substrate. A method for forming the organic semiconductor layer is provided. An evaporating source is provided, and the evaporating source and the insulating substrate are spaced from each other. The carbon nanotube film structure is heated to gasify the organic semiconductor material to form the organic semiconductor layer on a depositing surface.

The subject embodiments relate to carbon nanotube (CNT) transistors with carrier blocking using thin dielectric under the drain or source and drain contacts. According to an embodiment, a transistor is provided that comprises a CNT channel layer, a metal source contact formed on the carbon nanotube channel layer, and a metal drain contact formed on the carbon nanotube channel layer. The transistor structure further comprises a drain dielectric layer formed adjacent to and between a lower surface of the metal drain contact and an upper surface of the carbon nanotube channel layer. In one or more implementations, the drain dielectric layer comprises a material that suppresses injection of a first type of carrier into the CNT channel layer and facilitates the injection of a second type of carrier into the CNT channel layer.

The subject embodiments relate to carbon nanotube (CNT) transistors with carrier blocking using thin dielectric under the drain or source and drain contacts. According to an embodiment, a transistor is provided that comprises a CNT channel layer, a metal source contact formed on the carbon nanotube channel layer, and a metal drain contact formed on the carbon nanotube channel layer. The transistor structure further comprises a drain dielectric layer formed adjacent to and between a lower surface of the metal drain contact and an upper surface of the carbon nanotube channel layer. In one or more implementations, the drain dielectric layer comprises a material that suppresses injection of a first type of carrier into the CNT channel layer and facilitates the injection of a second type of carrier into the CNT channel layer.

In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

The present disclosure provides a transistor acoustic sensor element and a method for manufacturing the same, an acoustic sensor and a portable device. The transistor acoustic sensor element comprises a gate, a gate insulating layer, a first electrode, an active layer and a second electrode arranged on a base substrate, wherein the active layer has a nanowire three-dimensional mesh structure and thus can vibrate under the action of sound signals, so that the output current of the transistor acoustic sensor element changes correspondingly. Since the active layer having the nanowire three-dimensional mesh structure can sensitively sense weak vibration of acoustic waves, the sensitivity to sound signals of the transistor acoustic sensor element is improved.

A novel dibenzocarbazole compound with which a light-emitting element having low power consumption, high reliability, and high color purity can be fabricated is provided. In the dibenzocarbazole compound, an aryl group which has 14 to 30 carbon atoms and at least an anthracene skeleton is bonded to nitrogen of a dibenzo[a,g]carbazole skeleton or a dibenzo[a,i]carbazole skeleton. Furthermore, a light-emitting element including the dibenzocarbazole compound is provided.