An electronic device, such as a filter, includes a first substrate having a bottom surface and a top surface, a first side wall of a certain height being formed along a periphery of the bottom surface to surround an electronic circuit disposed on the bottom surface, an external electrode formed on the top surface, the external electrode being connected to the electronic circuit by a via communicating with the bottom surface and a second substrate. The second substrate has a second side wall of a certain height formed along a periphery of a top surface, the second side wall being aligned and bonded with the first side wall to internally form a cavity defined between the bottom surface of the first substrate, the top surface of the second substrate, the first side wall, and the second side wall.

A bonded body includes a supporting substrate; a piezoelectric material substrate composed of a material selected from the group consisting of lithium niobate, lithium tantalate and lithium niobate-lithium tantalate; and a bonding layer bonding the supporting substrate and the piezoelectric material substrate and contacting a main surface of the piezoelectric material substrate. The bonding layer includes a void extending from the piezoelectric material substrate to the supporting substrate.

A bonded body includes a supporting substrate; a piezoelectric material substrate composed of a material selected from the group consisting of lithium niobate, lithium tantalate and lithium niobate-lithium tantalate; and a bonding layer bonding the supporting substrate and the piezoelectric material substrate and contacting a main surface of the piezoelectric material substrate. The bonding layer includes a void extending from the piezoelectric material substrate toward the supporting substrate. A ratio (t2/t1) of a width t2 at an end of the void on a side of the supporting substrate with respect to a width t1 at an end of the void on a side of the piezoelectric material substrate is 0.8 or lower.

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic/solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.

The present disclosure provides methods to integrate pMUT arrays with an ASIC using solid liquid interdiffusion (SLID). In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT device and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using a conductive bonding pillar, which conductive bonding pillar comprises one or more intermetallic compounds. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT device and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using a conductive bonding pillar, wherein the bonding is performed at a temperature less than the melting point of the conductive bonding pillar after the bonding.

A bonded body includes a supporting substrate, a bonding layer provided on a surface of a supporting substrate and composed of silicon oxide, and a piezoelectric material substrate of a material selected from the group consisting of lithium niobate, lithium tantalate and lithium niobate-lithium tantalate. A convexity is provided on the surface of the supporting substrate, and the bonding layer includes a structural defect part extending above the convexity.

A sleep monitor includes a layered sensor that includes at least one substrate layer that includes multiple laterally adjacent substrates. The substrate layer may be formed by interdigitating fingers of a first sheet with fingers of a second sheet. Combining multiple substrates in a single layer of a layered sensor may allow multiple materials and/or sensing mechanisms to be combined together in a single layer.

A sensor system includes a sensor stack, a differential amplifier, an analog-to-digital converter, and a processor. The sensor stack includes a piezoelectric material having a first side opposing a second side, a first electrode connected to the first side, and a second electrode connected to the second side. The differential amplifier is coupled to the first and second electrodes and is configured to generate a differential output indicative of vibrations sensed by the piezoelectric material. The analog-to-differential converter is configured to digitize the differential output. The processor is configured to identify a type of biological vibration included in the digitized differential output.

Provided is a nano-scale single crystal thin film. The nano-scale single crystal thin film comprises a nano-scale single crystal thin film layer, a first transition layer, an isolation layer, a second transition layer, and a substrate layer. The first transition layer is located between the nano-scale single crystal thin film layer and the isolation layer, while the second transition layer is located between the isolation layer and the substrate layer. The first transition layer comprises a certain concentration of the H element.

A method for fabricating an array of front ends for an array of packaged electronic components that each comprise:

an electrical element packaged within a package comprising
a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and
a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a flip chip configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii. Obtaining an inner front end section; iii. Attaching the inner front end section to the exposed front surface of the front electrode; iv. Detaching the carrier substrate from the rear surface of the active membrane layer; v. Optionally thinning the inner front section; vi. Processing the rear surface by removing material to create an array of at least one island of active membrane on at least one island of front electrode; vii. Creating an array of at least one front cavity by selectively removing at least outer layer of the inner front end section, such that there is one cavity opposite each island of membrane on the front side of the front electrode on the opposite side to the island of active membrane; viii. Applying an outer front end section to the inner front end section and bonding the outer front end section to an outer surface of the inner front end section such that the outer front end section spans across and seals the at least one cavity of the array of front cavities.